Lines Matching refs:clocks
150 struct clk *clocks[MT8173_CLK_NUM];
328 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M],
330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M],
351 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
352 afe_priv->clocks[MT8173_CLK_I2S3_B]);
365 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
366 afe_priv->clocks[MT8173_CLK_I2S3_B]);
378 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M],
380 afe_priv->clocks[MT8173_CLK_I2S3_B],
960 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
961 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
962 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
963 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]);
964 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
965 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
966 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
976 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
980 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
984 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
988 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]);
992 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]);
995 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]);
998 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1017 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]);
1019 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]);
1021 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]);
1023 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]);
1025 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]);
1027 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]);
1037 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]);
1038 if (IS_ERR(afe_priv->clocks[i])) {
1041 return PTR_ERR(afe_priv->clocks[i]);
1044 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */
1045 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */