Lines Matching refs:clocks
280 * These are not hardware clocks, but are needed to handle the special
320 clk_rdesc_set(struct r9a06g032_priv *clocks,
323 u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
331 clk_rdesc_get(struct r9a06g032_priv *clocks,
334 u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
347 struct r9a06g032_priv *clocks;
389 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++,
434 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks,
441 spin_lock_irqsave(&clocks->lock, flags);
442 clk_rdesc_set(clocks, g->gate, on);
445 clk_rdesc_set(clocks, g->reset, 1);
446 spin_unlock_irqrestore(&clocks->lock, flags);
456 spin_lock_irqsave(&clocks->lock, flags);
458 clk_rdesc_set(clocks, g->ready, on);
461 clk_rdesc_set(clocks, g->midle, !on);
462 spin_unlock_irqrestore(&clocks->lock, flags);
471 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
479 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
487 if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))
490 return clk_rdesc_get(g->clocks, g->gate.gate);
500 r9a06g032_register_gate(struct r9a06g032_priv *clocks,
518 g->clocks = clocks;
524 * important here, some clocks are already in use by the CM3, we
543 struct r9a06g032_priv *clocks;
559 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
625 * The serial driver *shouldn't* play with these clocks anyway, there's
646 u32 __iomem *reg = clk->clocks->reg + (4 * clk->reg);
670 r9a06g032_register_div(struct r9a06g032_priv *clocks,
689 div->clocks = clocks;
712 * each of the clock source - the used clock source (for all sub clocks)
714 * That single bit affects all sub-clocks, and therefore needs to change the
723 struct r9a06g032_priv *clocks;
735 return clk_rdesc_get(set->clocks, set->selector);
742 /* a single bit in the register selects one of two parent clocks */
743 clk_rdesc_set(set->clocks, set->selector, !!index);
754 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks,
777 g->clocks = clocks;
792 struct r9a06g032_priv *clocks;
804 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
807 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
808 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
832 u8 sel_bit = clk_rdesc_get(g->clocks, g->selector);
834 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
844 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
857 g->clocks = clocks;
872 * important here, some clocks are already in use by the CM3, we
898 struct r9a06g032_priv *clocks;
905 clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
908 if (!clocks || !clks)
911 spin_lock_init(&clocks->lock);
913 clocks->data.clks = clks;
914 clocks->data.clk_num = R9A06G032_CLOCK_COUNT;
920 clocks->reg = of_iomap(np, 0);
921 if (WARN_ON(!clocks->reg))
926 __clk_get_name(clocks->data.clks[d->source - 1]) :
937 clk = r9a06g032_register_gate(clocks, parent_name, d);
940 clk = r9a06g032_register_div(clocks, parent_name, d);
945 clk = r9a06g032_register_bitsel(clocks, parent_name, d);
948 clk = r9a06g032_register_dualgate(clocks, parent_name,
953 clocks->data.clks[d->index] = clk;
955 error = of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);