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Searched refs:clkctrl_offs (Results 1 - 20 of 20) sorted by relevance

/kernel/linux/linux-5.10/arch/arm/mach-omap2/
H A Dcm33xx.c89 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
94 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument
96 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); in _clkctrl_idlest()
105 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
110 static bool _is_module_ready(u16 inst, u16 clkctrl_offs) in _is_module_ready() argument
114 v = _clkctrl_idlest(inst, clkctrl_offs); in _is_module_ready()
221 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
229 static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, in am33xx_cm_wait_module_ready() argument
234 omap_test_timeout(_is_module_ready(inst, clkctrl_offs), in am33xx_cm_wait_module_ready()
245 * @clkctrl_offs
252 am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, u8 bit_shift) am33xx_cm_wait_module_idle() argument
273 am33xx_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) am33xx_cm_module_enable() argument
292 am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) am33xx_cm_module_disable() argument
[all...]
H A Domap_hwmod_54xx_data.c48 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
69 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
83 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
96 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
109 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
131 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
144 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
157 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
206 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
222 .clkctrl_offs
[all...]
H A Domap_hwmod_81xx_data.c34 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
103 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
178 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
205 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
247 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
284 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
305 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
326 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
364 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
401 .clkctrl_offs
[all...]
H A Domap_hwmod_33xx_data.c39 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
54 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
74 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
112 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
132 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
150 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
177 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
193 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
H A Domap_hwmod_7xx_data.c48 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
69 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
83 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
96 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
118 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
131 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
144 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
157 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
170 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
193 .clkctrl_offs
[all...]
H A Dcm.h61 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
62 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
63 u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);
72 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
73 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
74 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
H A Domap_hwmod_44xx_data.c51 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
72 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
86 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
99 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
112 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
134 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
147 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
160 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
201 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
304 .clkctrl_offs
[all...]
H A Dcminst44xx.c80 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
85 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument
87 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); in _clkctrl_idlest()
97 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) in _is_module_ready() argument
106 v = _clkctrl_idlest(part, inst, clkctrl_offs); in _is_module_ready()
266 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
274 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, in omap4_cminst_wait_module_ready() argument
279 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), in omap4_cminst_wait_module_ready()
290 * @clkctrl_offs
297 omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, u8 bit_shift) omap4_cminst_wait_module_idle() argument
318 omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) omap4_cminst_module_enable() argument
337 omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs) omap4_cminst_module_disable() argument
[all...]
H A Dcm_common.c138 * @clkctrl_offs: CM_CLKCTRL register offset for the module
140 * Enables clocks for a module identified by (@part, @inst, @clkctrl_offs)
144 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_module_enable() argument
152 cm_ll_data->module_enable(mode, part, inst, clkctrl_offs); in omap_cm_module_enable()
160 * @clkctrl_offs: CM_CLKCTRL register offset for the module
162 * Disables clocks for a module identified by (@part, @inst, @clkctrl_offs)
166 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_module_disable() argument
174 cm_ll_data->module_disable(part, inst, clkctrl_offs); in omap_cm_module_disable()
178 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_xlate_clkctrl() argument
185 return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs); in omap_cm_xlate_clkctrl()
[all...]
H A Domap_hwmod_43xx_data.c31 .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
45 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
64 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
82 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
H A Domap_hwmod_33xx_43xx_ipblock_data.c26 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
H A Domap_hwmod.c768 oh->prcm.omap4.clkctrl_offs); in _omap4_xlate_clkctrl()
1018 if (oh->prcm.omap4.clkctrl_offs) in _omap4_has_clkctrl_clock()
1021 if (!oh->prcm.omap4.clkctrl_offs && in _omap4_has_clkctrl_clock()
1076 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); in _omap4_enable_module()
1107 oh->prcm.omap4.clkctrl_offs, 0); in _omap4_wait_target_disable()
1666 oh->prcm.omap4.clkctrl_offs); in _omap4_disable_module()
2743 oh->prcm.omap4.clkctrl_offs, 0); in _omap4_wait_target_ready()
H A Domap_hwmod.h361 * @clkctrl_offs: offset of the PRCM clock control register
377 u16 clkctrl_offs; member
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
H A Dcm33xx.c81 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
86 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument
88 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); in _clkctrl_idlest()
97 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 static bool _is_module_ready(u16 inst, u16 clkctrl_offs) in _is_module_ready() argument
106 v = _clkctrl_idlest(inst, clkctrl_offs); in _is_module_ready()
213 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
221 static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, in am33xx_cm_wait_module_ready() argument
226 omap_test_timeout(_is_module_ready(inst, clkctrl_offs), in am33xx_cm_wait_module_ready()
237 * @clkctrl_offs
244 am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, u8 bit_shift) am33xx_cm_wait_module_idle() argument
265 am33xx_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) am33xx_cm_module_enable() argument
284 am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) am33xx_cm_module_disable() argument
[all...]
H A Domap_hwmod_81xx_data.c25 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
94 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's
169 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL,
196 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL,
238 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL,
275 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL,
296 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL,
317 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL,
355 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL,
392 .clkctrl_offs
[all...]
H A Dcm.h60 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
61 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
62 u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs);
71 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
72 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
73 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs);
H A Dcminst44xx.c80 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
85 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs) in _clkctrl_idlest() argument
87 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs); in _clkctrl_idlest()
97 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs) in _is_module_ready() argument
106 v = _clkctrl_idlest(part, inst, clkctrl_offs); in _is_module_ready()
266 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
274 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs, in omap4_cminst_wait_module_ready() argument
279 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs), in omap4_cminst_wait_module_ready()
290 * @clkctrl_offs
297 omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs, u8 bit_shift) omap4_cminst_wait_module_idle() argument
318 omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) omap4_cminst_module_enable() argument
337 omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs) omap4_cminst_module_disable() argument
[all...]
H A Dcm_common.c125 * @clkctrl_offs: CM_CLKCTRL register offset for the module
127 * Enables clocks for a module identified by (@part, @inst, @clkctrl_offs)
131 int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_module_enable() argument
139 cm_ll_data->module_enable(mode, part, inst, clkctrl_offs); in omap_cm_module_enable()
147 * @clkctrl_offs: CM_CLKCTRL register offset for the module
149 * Disables clocks for a module identified by (@part, @inst, @clkctrl_offs)
153 int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_module_disable() argument
161 cm_ll_data->module_disable(part, inst, clkctrl_offs); in omap_cm_module_disable()
165 u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs) in omap_cm_xlate_clkctrl() argument
172 return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs); in omap_cm_xlate_clkctrl()
[all...]
H A Domap_hwmod.c768 oh->prcm.omap4.clkctrl_offs); in _omap4_xlate_clkctrl()
1018 if (oh->prcm.omap4.clkctrl_offs) in _omap4_has_clkctrl_clock()
1021 if (!oh->prcm.omap4.clkctrl_offs && in _omap4_has_clkctrl_clock()
1076 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); in _omap4_enable_module()
1107 oh->prcm.omap4.clkctrl_offs, 0); in _omap4_wait_target_disable()
1666 oh->prcm.omap4.clkctrl_offs); in _omap4_disable_module()
2711 oh->prcm.omap4.clkctrl_offs, 0); in _omap4_wait_target_ready()
H A Domap_hwmod.h361 * @clkctrl_offs: offset of the PRCM clock control register
377 u16 clkctrl_offs; member

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