Lines Matching refs:clkctrl_offs
80 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
85 static u32 _clkctrl_idlest(u8 part, u16 inst, u16 clkctrl_offs)
87 u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
97 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 static bool _is_module_ready(u8 part, u16 inst, u16 clkctrl_offs)
106 v = _clkctrl_idlest(part, inst, clkctrl_offs);
266 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
274 static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
279 omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
290 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
297 static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
302 omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) ==
314 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
319 u16 clkctrl_offs)
323 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
326 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
333 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
337 static void omap4_cminst_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
341 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
343 omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);