Lines Matching refs:clkctrl_offs
89 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
94 static u32 _clkctrl_idlest(u16 inst, u16 clkctrl_offs)
96 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
105 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
110 static bool _is_module_ready(u16 inst, u16 clkctrl_offs)
114 v = _clkctrl_idlest(inst, clkctrl_offs);
221 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
229 static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
234 omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
245 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
252 static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
257 omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
269 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
274 u16 clkctrl_offs)
278 v = am33xx_cm_read_reg(inst, clkctrl_offs);
281 am33xx_cm_write_reg(v, inst, clkctrl_offs);
288 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
292 static void am33xx_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs)
296 v = am33xx_cm_read_reg(inst, clkctrl_offs);
298 am33xx_cm_write_reg(v, inst, clkctrl_offs);