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Searched refs:cha_num (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h309 /* Channel Registers, cha_num = 0-15 */
312 #define SXGBE_DMA_CHA_CTL_REG(cha_num) \
313 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x00)
316 #define SXGBE_DMA_CHA_TXCTL_REG(cha_num) \
317 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x04)
318 #define SXGBE_DMA_CHA_RXCTL_REG(cha_num) \
319 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x08)
320 #define SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num) \
321 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x10)
322 #define SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num) \
[all...]
H A Dsxgbe_dma.c43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, in sxgbe_dma_channel_init() argument
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
60 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
62 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
67 ioaddr + SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
69 ioaddr + SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
72 ioaddr + SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
96 sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) sxgbe_enable_dma_transmission() argument
[all...]
H A Dsxgbe_dma.h23 void (*cha_init)(void __iomem *ioaddr, int cha_num, int fix_burst,
/kernel/linux/linux-6.6/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_reg.h309 /* Channel Registers, cha_num = 0-15 */
312 #define SXGBE_DMA_CHA_CTL_REG(cha_num) \
313 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x00)
316 #define SXGBE_DMA_CHA_TXCTL_REG(cha_num) \
317 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x04)
318 #define SXGBE_DMA_CHA_RXCTL_REG(cha_num) \
319 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x08)
320 #define SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num) \
321 (SXGBE_DMA_CHA_BASE_REG + (cha_num * 0x80) + 0x10)
322 #define SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num) \
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H A Dsxgbe_dma.c43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, in sxgbe_dma_channel_init() argument
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
60 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
62 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
67 ioaddr + SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
69 ioaddr + SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
72 ioaddr + SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
96 sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) sxgbe_enable_dma_transmission() argument
[all...]
H A Dsxgbe_dma.h23 void (*cha_init)(void __iomem *ioaddr, int cha_num, int fix_burst,

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