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Searched refs:Op1 (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-6.6/arch/arm64/kvm/
H A Dsys_regs.h17 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
22 u8 Op1; member
32 .Op1 = sys_reg_Op1(reg), \
39 .Op1 = ((esr) >> 14) & 0x7, \
46 ((struct sys_reg_params){ .Op1 = ((esr) >> 14) & 0x7, \
64 u8 Op1; member
110 kvm_pr_unimpl("%pV { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n", in print_sys_reg_msg()
112 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_msg()
199 if (i1->Op1 != i2->Op1) in cmp_sys_reg()
238 #define Op1 global() macro
[all...]
H A Dsys_regs.c315 switch (p->Op1) { in access_gic_sgi()
1366 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
1844 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1848 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1910 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
2464 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
2466 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
2468 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
2470 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
2473 { AA32(HI), Op1(
[all...]
H A Dtrace_handle_exit.h169 __field(u8, Op1)
181 __entry->Op1 = reg->Op1;
189 __entry->Op0, __entry->Op1, __entry->CRn,
/kernel/linux/linux-5.10/arch/arm64/kvm/
H A Dsys_regs.h16 u8 Op1; member
32 u8 Op1; member
73 kvm_pr_unimpl("%pV { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n", in print_sys_reg_msg()
75 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_msg()
142 if (i1->Op1 != i2->Op1) in cmp_sys_reg()
143 return i1->Op1 - i2->Op1; in cmp_sys_reg()
157 #define Op1(_x) .Op1 macro
[all...]
H A Dsys_regs.c295 switch (p->Op1) { in access_gic_sgi()
355 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, in trap_loregion()
1027 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
1125 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, in read_id_reg()
1160 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, in id_visibility()
1390 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1394 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1414 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1864 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1866 { Op1(
[all...]
H A Dtrace_handle_exit.h165 __field(u8, Op1)
177 __entry->Op1 = reg->Op1;
185 __entry->Op0, __entry->Op1, __entry->CRn,
/kernel/linux/linux-5.10/arch/arm/include/asm/vdso/
H A Dcp15.h14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
16 #define __ACCESS_CP15_64(Op1, CRm) \
17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
/kernel/linux/linux-6.6/arch/arm/include/asm/vdso/
H A Dcp15.h14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
16 #define __ACCESS_CP15_64(Op1, CRm) \
17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
/kernel/liteos_a/arch/arm/arm/include/
H A Dlos_hw_cpu.h85 #define CP14_REG(CRn, Op1, CRm, Op2) "p14, "#Op1", %0, "#CRn","#CRm","#Op2
86 #define CP15_REG(CRn, Op1, CRm, Op2) "p15, "#Op1", %0, "#CRn","#CRm","#Op2
87 #define CP15_REG64(CRn, Op1) "p15, "#Op1", %0, %H0,"#CRn
/kernel/linux/linux-6.6/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c323 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
327 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
339 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2

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