Lines Matching refs:Op1
315 switch (p->Op1) {
1366 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
1844 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1848 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1910 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
2464 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
2466 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
2468 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
2470 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
2473 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
2482 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
2484 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
2488 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
2491 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
2493 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
2496 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
2498 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
2503 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
2505 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
2508 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
2520 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
2524 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
2527 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
2531 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
2534 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
2548 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
2551 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
2553 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
2555 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
2557 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
2559 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
2561 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
2567 { Op1( 0), CRm( 1), .access = trap_raz_wi },
2570 { Op1( 0), CRm( 2), .access = trap_raz_wi },
2575 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
2595 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
2596 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
2598 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
2600 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
2601 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2602 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
2604 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2606 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
2607 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2609 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
2610 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
2612 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
2614 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2616 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2618 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
2623 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2624 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2625 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2649 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2651 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2653 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2655 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2658 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2660 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2733 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2734 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2737 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },
2739 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2743 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2745 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2747 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2748 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2749 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2878 params.Op1 = (esr >> 16) & 0xf;
2924 params->Op1 = 0;
3068 if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
3215 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
3490 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |