Lines Matching refs:Op1
295 switch (p->Op1) {
355 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
1027 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
1125 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1160 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1390 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1394 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1414 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1864 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1866 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1868 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1870 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1873 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1882 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1884 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1888 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1891 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
1893 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
1896 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1898 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1903 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1905 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1908 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
1920 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1924 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1927 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1931 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1934 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1948 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1951 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1953 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1955 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1957 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1959 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1961 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1967 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1970 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1976 { Op1(0), CRn(0b1110), \
1983 { Op1(0), CRn(0b1110), \
1993 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1994 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1995 { Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr },
1996 { Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr },
1997 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1998 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1999 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
2000 { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
2001 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
2002 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
2003 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
2004 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
2005 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
2006 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
2007 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
2012 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2013 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2014 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2017 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
2018 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
2019 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
2020 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
2021 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
2022 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
2023 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
2024 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
2025 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
2026 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
2027 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
2028 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
2029 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
2030 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
2031 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
2033 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
2034 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
2035 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
2036 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
2039 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2041 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
2112 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2114 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2115 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2116 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
2120 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
2121 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2122 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2123 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
2124 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2125 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2273 params.Op1 = (esr >> 16) & 0xf;
2325 params.Op1 = (esr >> 14) & 0x7;
2416 params.Op1 = (esr >> 14) & 0x7;
2449 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2745 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |