1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bsearch.h>
13 #include <linux/kvm_host.h>
14 #include <linux/mm.h>
15 #include <linux/printk.h>
16 #include <linux/uaccess.h>
17
18 #include <asm/cacheflush.h>
19 #include <asm/cputype.h>
20 #include <asm/debug-monitors.h>
21 #include <asm/esr.h>
22 #include <asm/kvm_arm.h>
23 #include <asm/kvm_coproc.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_hyp.h>
26 #include <asm/kvm_mmu.h>
27 #include <asm/perf_event.h>
28 #include <asm/sysreg.h>
29
30 #include <trace/events/kvm.h>
31
32 #include "sys_regs.h"
33 #include "vgic/vgic.h"
34
35 #include "trace.h"
36
37 /*
38 * All of this file is extremely similar to the ARM coproc.c, but the
39 * types are different. My gut feeling is that it should be pretty
40 * easy to merge, but that would be an ABI breakage -- again. VFP
41 * would also need to be abstracted.
42 *
43 * For AArch32, we only take care of what is being trapped. Anything
44 * that has to do with init and userspace access has to go via the
45 * 64bit interface.
46 */
47
read_from_write_only(struct kvm_vcpu *vcpu, struct sys_reg_params *params, const struct sys_reg_desc *r)48 static bool read_from_write_only(struct kvm_vcpu *vcpu,
49 struct sys_reg_params *params,
50 const struct sys_reg_desc *r)
51 {
52 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
53 print_sys_reg_instr(params);
54 kvm_inject_undefined(vcpu);
55 return false;
56 }
57
write_to_read_only(struct kvm_vcpu *vcpu, struct sys_reg_params *params, const struct sys_reg_desc *r)58 static bool write_to_read_only(struct kvm_vcpu *vcpu,
59 struct sys_reg_params *params,
60 const struct sys_reg_desc *r)
61 {
62 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
63 print_sys_reg_instr(params);
64 kvm_inject_undefined(vcpu);
65 return false;
66 }
67
__vcpu_read_sys_reg_from_cpu(int reg, u64 *val)68 static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
69 {
70 /*
71 * System registers listed in the switch are not saved on every
72 * exit from the guest but are only saved on vcpu_put.
73 *
74 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
75 * should never be listed below, because the guest cannot modify its
76 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
77 * thread when emulating cross-VCPU communication.
78 */
79 switch (reg) {
80 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break;
81 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
82 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
83 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
84 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
85 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
86 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
87 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
88 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
89 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
90 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
91 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
92 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
93 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
94 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
95 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
96 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
97 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
98 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
99 case PAR_EL1: *val = read_sysreg_par(); break;
100 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
101 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
102 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
103 default: return false;
104 }
105
106 return true;
107 }
108
__vcpu_write_sys_reg_to_cpu(u64 val, int reg)109 static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
110 {
111 /*
112 * System registers listed in the switch are not restored on every
113 * entry to the guest but are only restored on vcpu_load.
114 *
115 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
116 * should never be listed below, because the MPIDR should only be set
117 * once, before running the VCPU, and never changed later.
118 */
119 switch (reg) {
120 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break;
121 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
122 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
123 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
124 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
125 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
126 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
127 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
128 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
129 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
130 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
131 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
132 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
133 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
134 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
135 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
136 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
137 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
138 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
139 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
140 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
141 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
142 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
143 default: return false;
144 }
145
146 return true;
147 }
148
vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)149 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
150 {
151 u64 val = 0x8badf00d8badf00d;
152
153 if (vcpu->arch.sysregs_loaded_on_cpu &&
154 __vcpu_read_sys_reg_from_cpu(reg, &val))
155 return val;
156
157 return __vcpu_sys_reg(vcpu, reg);
158 }
159
vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)160 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
161 {
162 if (vcpu->arch.sysregs_loaded_on_cpu &&
163 __vcpu_write_sys_reg_to_cpu(val, reg))
164 return;
165
166 __vcpu_sys_reg(vcpu, reg) = val;
167 }
168
169 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
170 static u32 cache_levels;
171
172 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
173 #define CSSELR_MAX 12
174
175 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(u32 csselr)176 static u32 get_ccsidr(u32 csselr)
177 {
178 u32 ccsidr;
179
180 /* Make sure noone else changes CSSELR during this! */
181 local_irq_disable();
182 write_sysreg(csselr, csselr_el1);
183 isb();
184 ccsidr = read_sysreg(ccsidr_el1);
185 local_irq_enable();
186
187 return ccsidr;
188 }
189
190 /*
191 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
192 */
access_dcsw(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)193 static bool access_dcsw(struct kvm_vcpu *vcpu,
194 struct sys_reg_params *p,
195 const struct sys_reg_desc *r)
196 {
197 if (!p->is_write)
198 return read_from_write_only(vcpu, p, r);
199
200 /*
201 * Only track S/W ops if we don't have FWB. It still indicates
202 * that the guest is a bit broken (S/W operations should only
203 * be done by firmware, knowing that there is only a single
204 * CPU left in the system, and certainly not from non-secure
205 * software).
206 */
207 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
208 kvm_set_way_flush(vcpu);
209
210 return true;
211 }
212
213 /*
214 * Generic accessor for VM registers. Only called as long as HCR_TVM
215 * is set. If the guest enables the MMU, we stop trapping the VM
216 * sys_regs and leave it in complete control of the caches.
217 */
access_vm_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)218 static bool access_vm_reg(struct kvm_vcpu *vcpu,
219 struct sys_reg_params *p,
220 const struct sys_reg_desc *r)
221 {
222 bool was_enabled = vcpu_has_cache_enabled(vcpu);
223 u64 val;
224 int reg = r->reg;
225
226 BUG_ON(!p->is_write);
227
228 /* See the 32bit mapping in kvm_host.h */
229 if (p->is_aarch32)
230 reg = r->reg / 2;
231
232 if (!p->is_aarch32 || !p->is_32bit) {
233 val = p->regval;
234 } else {
235 val = vcpu_read_sys_reg(vcpu, reg);
236 if (r->reg % 2)
237 val = (p->regval << 32) | (u64)lower_32_bits(val);
238 else
239 val = ((u64)upper_32_bits(val) << 32) |
240 lower_32_bits(p->regval);
241 }
242 vcpu_write_sys_reg(vcpu, val, reg);
243
244 kvm_toggle_cache(vcpu, was_enabled);
245 return true;
246 }
247
access_actlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)248 static bool access_actlr(struct kvm_vcpu *vcpu,
249 struct sys_reg_params *p,
250 const struct sys_reg_desc *r)
251 {
252 if (p->is_write)
253 return ignore_write(vcpu, p);
254
255 p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1);
256
257 if (p->is_aarch32) {
258 if (r->Op2 & 2)
259 p->regval = upper_32_bits(p->regval);
260 else
261 p->regval = lower_32_bits(p->regval);
262 }
263
264 return true;
265 }
266
267 /*
268 * Trap handler for the GICv3 SGI generation system register.
269 * Forward the request to the VGIC emulation.
270 * The cp15_64 code makes sure this automatically works
271 * for both AArch64 and AArch32 accesses.
272 */
access_gic_sgi(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)273 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
274 struct sys_reg_params *p,
275 const struct sys_reg_desc *r)
276 {
277 bool g1;
278
279 if (!kvm_has_gicv3(vcpu->kvm)) {
280 kvm_inject_undefined(vcpu);
281 return false;
282 }
283
284 if (!p->is_write)
285 return read_from_write_only(vcpu, p, r);
286
287 /*
288 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
289 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
290 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
291 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
292 * group.
293 */
294 if (p->is_aarch32) {
295 switch (p->Op1) {
296 default: /* Keep GCC quiet */
297 case 0: /* ICC_SGI1R */
298 g1 = true;
299 break;
300 case 1: /* ICC_ASGI1R */
301 case 2: /* ICC_SGI0R */
302 g1 = false;
303 break;
304 }
305 } else {
306 switch (p->Op2) {
307 default: /* Keep GCC quiet */
308 case 5: /* ICC_SGI1R_EL1 */
309 g1 = true;
310 break;
311 case 6: /* ICC_ASGI1R_EL1 */
312 case 7: /* ICC_SGI0R_EL1 */
313 g1 = false;
314 break;
315 }
316 }
317
318 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
319
320 return true;
321 }
322
access_gic_sre(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)323 static bool access_gic_sre(struct kvm_vcpu *vcpu,
324 struct sys_reg_params *p,
325 const struct sys_reg_desc *r)
326 {
327 if (p->is_write)
328 return ignore_write(vcpu, p);
329
330 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
331 return true;
332 }
333
trap_raz_wi(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)334 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
335 struct sys_reg_params *p,
336 const struct sys_reg_desc *r)
337 {
338 if (p->is_write)
339 return ignore_write(vcpu, p);
340 else
341 return read_zero(vcpu, p);
342 }
343
344 /*
345 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
346 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
347 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
348 * treat it separately.
349 */
trap_loregion(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)350 static bool trap_loregion(struct kvm_vcpu *vcpu,
351 struct sys_reg_params *p,
352 const struct sys_reg_desc *r)
353 {
354 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
355 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
356 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
357
358 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
359 kvm_inject_undefined(vcpu);
360 return false;
361 }
362
363 if (p->is_write && sr == SYS_LORID_EL1)
364 return write_to_read_only(vcpu, p, r);
365
366 return trap_raz_wi(vcpu, p, r);
367 }
368
trap_oslsr_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)369 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
370 struct sys_reg_params *p,
371 const struct sys_reg_desc *r)
372 {
373 if (p->is_write) {
374 return ignore_write(vcpu, p);
375 } else {
376 p->regval = (1 << 3);
377 return true;
378 }
379 }
380
trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)381 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
382 struct sys_reg_params *p,
383 const struct sys_reg_desc *r)
384 {
385 if (p->is_write) {
386 return ignore_write(vcpu, p);
387 } else {
388 p->regval = read_sysreg(dbgauthstatus_el1);
389 return true;
390 }
391 }
392
393 /*
394 * We want to avoid world-switching all the DBG registers all the
395 * time:
396 *
397 * - If we've touched any debug register, it is likely that we're
398 * going to touch more of them. It then makes sense to disable the
399 * traps and start doing the save/restore dance
400 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
401 * then mandatory to save/restore the registers, as the guest
402 * depends on them.
403 *
404 * For this, we use a DIRTY bit, indicating the guest has modified the
405 * debug registers, used as follow:
406 *
407 * On guest entry:
408 * - If the dirty bit is set (because we're coming back from trapping),
409 * disable the traps, save host registers, restore guest registers.
410 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
411 * set the dirty bit, disable the traps, save host registers,
412 * restore guest registers.
413 * - Otherwise, enable the traps
414 *
415 * On guest exit:
416 * - If the dirty bit is set, save guest registers, restore host
417 * registers and clear the dirty bit. This ensure that the host can
418 * now use the debug registers.
419 */
trap_debug_regs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)420 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
421 struct sys_reg_params *p,
422 const struct sys_reg_desc *r)
423 {
424 if (p->is_write) {
425 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
426 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
427 } else {
428 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
429 }
430
431 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
432
433 return true;
434 }
435
436 /*
437 * reg_to_dbg/dbg_to_reg
438 *
439 * A 32 bit write to a debug register leave top bits alone
440 * A 32 bit read from a debug register only returns the bottom bits
441 *
442 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
443 * hyp.S code switches between host and guest values in future.
444 */
reg_to_dbg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, u64 *dbg_reg)445 static void reg_to_dbg(struct kvm_vcpu *vcpu,
446 struct sys_reg_params *p,
447 u64 *dbg_reg)
448 {
449 u64 val = p->regval;
450
451 if (p->is_32bit) {
452 val &= 0xffffffffUL;
453 val |= ((*dbg_reg >> 32) << 32);
454 }
455
456 *dbg_reg = val;
457 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
458 }
459
dbg_to_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, u64 *dbg_reg)460 static void dbg_to_reg(struct kvm_vcpu *vcpu,
461 struct sys_reg_params *p,
462 u64 *dbg_reg)
463 {
464 p->regval = *dbg_reg;
465 if (p->is_32bit)
466 p->regval &= 0xffffffffUL;
467 }
468
trap_bvr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd)469 static bool trap_bvr(struct kvm_vcpu *vcpu,
470 struct sys_reg_params *p,
471 const struct sys_reg_desc *rd)
472 {
473 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
474
475 if (p->is_write)
476 reg_to_dbg(vcpu, p, dbg_reg);
477 else
478 dbg_to_reg(vcpu, p, dbg_reg);
479
480 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
481
482 return true;
483 }
484
set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)485 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
486 const struct kvm_one_reg *reg, void __user *uaddr)
487 {
488 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
489
490 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
491 return -EFAULT;
492 return 0;
493 }
494
get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)495 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
496 const struct kvm_one_reg *reg, void __user *uaddr)
497 {
498 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
499
500 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
501 return -EFAULT;
502 return 0;
503 }
504
reset_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)505 static void reset_bvr(struct kvm_vcpu *vcpu,
506 const struct sys_reg_desc *rd)
507 {
508 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
509 }
510
trap_bcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd)511 static bool trap_bcr(struct kvm_vcpu *vcpu,
512 struct sys_reg_params *p,
513 const struct sys_reg_desc *rd)
514 {
515 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
516
517 if (p->is_write)
518 reg_to_dbg(vcpu, p, dbg_reg);
519 else
520 dbg_to_reg(vcpu, p, dbg_reg);
521
522 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
523
524 return true;
525 }
526
set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)527 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
528 const struct kvm_one_reg *reg, void __user *uaddr)
529 {
530 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
531
532 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
533 return -EFAULT;
534
535 return 0;
536 }
537
get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)538 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
539 const struct kvm_one_reg *reg, void __user *uaddr)
540 {
541 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
542
543 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
544 return -EFAULT;
545 return 0;
546 }
547
reset_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)548 static void reset_bcr(struct kvm_vcpu *vcpu,
549 const struct sys_reg_desc *rd)
550 {
551 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
552 }
553
trap_wvr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd)554 static bool trap_wvr(struct kvm_vcpu *vcpu,
555 struct sys_reg_params *p,
556 const struct sys_reg_desc *rd)
557 {
558 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
559
560 if (p->is_write)
561 reg_to_dbg(vcpu, p, dbg_reg);
562 else
563 dbg_to_reg(vcpu, p, dbg_reg);
564
565 trace_trap_reg(__func__, rd->CRm, p->is_write,
566 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
567
568 return true;
569 }
570
set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)571 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
572 const struct kvm_one_reg *reg, void __user *uaddr)
573 {
574 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
575
576 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
577 return -EFAULT;
578 return 0;
579 }
580
get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)581 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
582 const struct kvm_one_reg *reg, void __user *uaddr)
583 {
584 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
585
586 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
587 return -EFAULT;
588 return 0;
589 }
590
reset_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)591 static void reset_wvr(struct kvm_vcpu *vcpu,
592 const struct sys_reg_desc *rd)
593 {
594 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
595 }
596
trap_wcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd)597 static bool trap_wcr(struct kvm_vcpu *vcpu,
598 struct sys_reg_params *p,
599 const struct sys_reg_desc *rd)
600 {
601 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
602
603 if (p->is_write)
604 reg_to_dbg(vcpu, p, dbg_reg);
605 else
606 dbg_to_reg(vcpu, p, dbg_reg);
607
608 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
609
610 return true;
611 }
612
set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)613 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
614 const struct kvm_one_reg *reg, void __user *uaddr)
615 {
616 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
617
618 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
619 return -EFAULT;
620 return 0;
621 }
622
get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)623 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
624 const struct kvm_one_reg *reg, void __user *uaddr)
625 {
626 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
627
628 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
629 return -EFAULT;
630 return 0;
631 }
632
reset_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)633 static void reset_wcr(struct kvm_vcpu *vcpu,
634 const struct sys_reg_desc *rd)
635 {
636 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
637 }
638
reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)639 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
640 {
641 u64 amair = read_sysreg(amair_el1);
642 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
643 }
644
reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)645 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
646 {
647 u64 actlr = read_sysreg(actlr_el1);
648 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
649 }
650
reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)651 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
652 {
653 u64 mpidr;
654
655 /*
656 * Map the vcpu_id into the first three affinity level fields of
657 * the MPIDR. We limit the number of VCPUs in level 0 due to a
658 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
659 * of the GICv3 to be able to address each CPU directly when
660 * sending IPIs.
661 */
662 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
663 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
664 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
665 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
666 }
667
reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)668 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
669 {
670 u64 pmcr, val;
671
672 /* No PMU available, PMCR_EL0 may UNDEF... */
673 if (!kvm_arm_support_pmu_v3())
674 return;
675
676 pmcr = read_sysreg(pmcr_el0);
677 /*
678 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
679 * except PMCR.E resetting to zero.
680 */
681 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
682 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
683 if (!system_supports_32bit_el0())
684 val |= ARMV8_PMU_PMCR_LC;
685 __vcpu_sys_reg(vcpu, r->reg) = val;
686 }
687
check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)688 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
689 {
690 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
691 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
692
693 if (!enabled)
694 kvm_inject_undefined(vcpu);
695
696 return !enabled;
697 }
698
pmu_access_el0_disabled(struct kvm_vcpu *vcpu)699 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
700 {
701 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
702 }
703
pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)704 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
705 {
706 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
707 }
708
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)709 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
710 {
711 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
712 }
713
pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)714 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
715 {
716 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
717 }
718
access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)719 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
720 const struct sys_reg_desc *r)
721 {
722 u64 val;
723
724 if (!kvm_arm_pmu_v3_ready(vcpu))
725 return trap_raz_wi(vcpu, p, r);
726
727 if (pmu_access_el0_disabled(vcpu))
728 return false;
729
730 if (p->is_write) {
731 /* Only update writeable bits of PMCR */
732 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
733 val &= ~ARMV8_PMU_PMCR_MASK;
734 val |= p->regval & ARMV8_PMU_PMCR_MASK;
735 if (!system_supports_32bit_el0())
736 val |= ARMV8_PMU_PMCR_LC;
737 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
738 kvm_pmu_handle_pmcr(vcpu, val);
739 kvm_vcpu_pmu_restore_guest(vcpu);
740 } else {
741 /* PMCR.P & PMCR.C are RAZ */
742 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
743 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
744 p->regval = val;
745 }
746
747 return true;
748 }
749
access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)750 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
751 const struct sys_reg_desc *r)
752 {
753 if (!kvm_arm_pmu_v3_ready(vcpu))
754 return trap_raz_wi(vcpu, p, r);
755
756 if (pmu_access_event_counter_el0_disabled(vcpu))
757 return false;
758
759 if (p->is_write)
760 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
761 else
762 /* return PMSELR.SEL field */
763 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
764 & ARMV8_PMU_COUNTER_MASK;
765
766 return true;
767 }
768
access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)769 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
770 const struct sys_reg_desc *r)
771 {
772 u64 pmceid;
773
774 if (!kvm_arm_pmu_v3_ready(vcpu))
775 return trap_raz_wi(vcpu, p, r);
776
777 BUG_ON(p->is_write);
778
779 if (pmu_access_el0_disabled(vcpu))
780 return false;
781
782 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
783
784 p->regval = pmceid;
785
786 return true;
787 }
788
pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)789 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
790 {
791 u64 pmcr, val;
792
793 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
794 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
795 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
796 kvm_inject_undefined(vcpu);
797 return false;
798 }
799
800 return true;
801 }
802
access_pmu_evcntr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)803 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
804 struct sys_reg_params *p,
805 const struct sys_reg_desc *r)
806 {
807 u64 idx;
808
809 if (!kvm_arm_pmu_v3_ready(vcpu))
810 return trap_raz_wi(vcpu, p, r);
811
812 if (r->CRn == 9 && r->CRm == 13) {
813 if (r->Op2 == 2) {
814 /* PMXEVCNTR_EL0 */
815 if (pmu_access_event_counter_el0_disabled(vcpu))
816 return false;
817
818 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
819 & ARMV8_PMU_COUNTER_MASK;
820 } else if (r->Op2 == 0) {
821 /* PMCCNTR_EL0 */
822 if (pmu_access_cycle_counter_el0_disabled(vcpu))
823 return false;
824
825 idx = ARMV8_PMU_CYCLE_IDX;
826 } else {
827 return false;
828 }
829 } else if (r->CRn == 0 && r->CRm == 9) {
830 /* PMCCNTR */
831 if (pmu_access_event_counter_el0_disabled(vcpu))
832 return false;
833
834 idx = ARMV8_PMU_CYCLE_IDX;
835 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
836 /* PMEVCNTRn_EL0 */
837 if (pmu_access_event_counter_el0_disabled(vcpu))
838 return false;
839
840 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
841 } else {
842 return false;
843 }
844
845 if (!pmu_counter_idx_valid(vcpu, idx))
846 return false;
847
848 if (p->is_write) {
849 if (pmu_access_el0_disabled(vcpu))
850 return false;
851
852 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
853 } else {
854 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
855 }
856
857 return true;
858 }
859
access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)860 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
861 const struct sys_reg_desc *r)
862 {
863 u64 idx, reg;
864
865 if (!kvm_arm_pmu_v3_ready(vcpu))
866 return trap_raz_wi(vcpu, p, r);
867
868 if (pmu_access_el0_disabled(vcpu))
869 return false;
870
871 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
872 /* PMXEVTYPER_EL0 */
873 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
874 reg = PMEVTYPER0_EL0 + idx;
875 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
876 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
877 if (idx == ARMV8_PMU_CYCLE_IDX)
878 reg = PMCCFILTR_EL0;
879 else
880 /* PMEVTYPERn_EL0 */
881 reg = PMEVTYPER0_EL0 + idx;
882 } else {
883 BUG();
884 }
885
886 if (!pmu_counter_idx_valid(vcpu, idx))
887 return false;
888
889 if (p->is_write) {
890 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
891 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
892 kvm_vcpu_pmu_restore_guest(vcpu);
893 } else {
894 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
895 }
896
897 return true;
898 }
899
access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)900 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
901 const struct sys_reg_desc *r)
902 {
903 u64 val, mask;
904
905 if (!kvm_arm_pmu_v3_ready(vcpu))
906 return trap_raz_wi(vcpu, p, r);
907
908 if (pmu_access_el0_disabled(vcpu))
909 return false;
910
911 mask = kvm_pmu_valid_counter_mask(vcpu);
912 if (p->is_write) {
913 val = p->regval & mask;
914 if (r->Op2 & 0x1) {
915 /* accessing PMCNTENSET_EL0 */
916 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
917 kvm_pmu_enable_counter_mask(vcpu, val);
918 kvm_vcpu_pmu_restore_guest(vcpu);
919 } else {
920 /* accessing PMCNTENCLR_EL0 */
921 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
922 kvm_pmu_disable_counter_mask(vcpu, val);
923 }
924 } else {
925 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
926 }
927
928 return true;
929 }
930
access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)931 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
932 const struct sys_reg_desc *r)
933 {
934 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
935
936 if (!kvm_arm_pmu_v3_ready(vcpu))
937 return trap_raz_wi(vcpu, p, r);
938
939 if (!vcpu_mode_priv(vcpu)) {
940 kvm_inject_undefined(vcpu);
941 return false;
942 }
943
944 if (p->is_write) {
945 u64 val = p->regval & mask;
946
947 if (r->Op2 & 0x1)
948 /* accessing PMINTENSET_EL1 */
949 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
950 else
951 /* accessing PMINTENCLR_EL1 */
952 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
953 } else {
954 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
955 }
956
957 return true;
958 }
959
access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)960 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
961 const struct sys_reg_desc *r)
962 {
963 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
964
965 if (!kvm_arm_pmu_v3_ready(vcpu))
966 return trap_raz_wi(vcpu, p, r);
967
968 if (pmu_access_el0_disabled(vcpu))
969 return false;
970
971 if (p->is_write) {
972 if (r->CRm & 0x2)
973 /* accessing PMOVSSET_EL0 */
974 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
975 else
976 /* accessing PMOVSCLR_EL0 */
977 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
978 } else {
979 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
980 }
981
982 return true;
983 }
984
access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)985 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
986 const struct sys_reg_desc *r)
987 {
988 u64 mask;
989
990 if (!kvm_arm_pmu_v3_ready(vcpu))
991 return trap_raz_wi(vcpu, p, r);
992
993 if (!p->is_write)
994 return read_from_write_only(vcpu, p, r);
995
996 if (pmu_write_swinc_el0_disabled(vcpu))
997 return false;
998
999 mask = kvm_pmu_valid_counter_mask(vcpu);
1000 kvm_pmu_software_increment(vcpu, p->regval & mask);
1001 return true;
1002 }
1003
access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1004 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1005 const struct sys_reg_desc *r)
1006 {
1007 if (!kvm_arm_pmu_v3_ready(vcpu))
1008 return trap_raz_wi(vcpu, p, r);
1009
1010 if (p->is_write) {
1011 if (!vcpu_mode_priv(vcpu)) {
1012 kvm_inject_undefined(vcpu);
1013 return false;
1014 }
1015
1016 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1017 p->regval & ARMV8_PMU_USERENR_MASK;
1018 } else {
1019 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
1020 & ARMV8_PMU_USERENR_MASK;
1021 }
1022
1023 return true;
1024 }
1025
1026 #define reg_to_encoding(x) \
1027 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
1028 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
1029
1030 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1031 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
1032 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
1033 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
1034 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
1035 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
1036 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
1037 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
1038 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
1039 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
1040
1041 /* Macro to expand the PMEVCNTRn_EL0 register */
1042 #define PMU_PMEVCNTR_EL0(n) \
1043 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
1044 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
1045
1046 /* Macro to expand the PMEVTYPERn_EL0 register */
1047 #define PMU_PMEVTYPER_EL0(n) \
1048 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
1049 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
1050
undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1051 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1052 const struct sys_reg_desc *r)
1053 {
1054 kvm_inject_undefined(vcpu);
1055
1056 return false;
1057 }
1058
1059 /* Macro to expand the AMU counter and type registers*/
1060 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1061 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1062 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1063 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1064
ptrauth_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)1065 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1066 const struct sys_reg_desc *rd)
1067 {
1068 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1069 }
1070
1071 /*
1072 * If we land here on a PtrAuth access, that is because we didn't
1073 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1074 * way this happens is when the guest does not have PtrAuth support
1075 * enabled.
1076 */
1077 #define __PTRAUTH_KEY(k) \
1078 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1079 .visibility = ptrauth_visibility}
1080
1081 #define PTRAUTH_KEY(k) \
1082 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1083 __PTRAUTH_KEY(k ## KEYHI_EL1)
1084
access_arch_timer(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1085 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1086 struct sys_reg_params *p,
1087 const struct sys_reg_desc *r)
1088 {
1089 enum kvm_arch_timers tmr;
1090 enum kvm_arch_timer_regs treg;
1091 u64 reg = reg_to_encoding(r);
1092
1093 switch (reg) {
1094 case SYS_CNTP_TVAL_EL0:
1095 case SYS_AARCH32_CNTP_TVAL:
1096 tmr = TIMER_PTIMER;
1097 treg = TIMER_REG_TVAL;
1098 break;
1099 case SYS_CNTP_CTL_EL0:
1100 case SYS_AARCH32_CNTP_CTL:
1101 tmr = TIMER_PTIMER;
1102 treg = TIMER_REG_CTL;
1103 break;
1104 case SYS_CNTP_CVAL_EL0:
1105 case SYS_AARCH32_CNTP_CVAL:
1106 tmr = TIMER_PTIMER;
1107 treg = TIMER_REG_CVAL;
1108 break;
1109 default:
1110 BUG();
1111 }
1112
1113 if (p->is_write)
1114 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1115 else
1116 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1117
1118 return true;
1119 }
1120
1121 /* Read a sanitised cpufeature ID register by sys_reg_desc */
read_id_reg(const struct kvm_vcpu *vcpu, struct sys_reg_desc const *r, bool raz)1122 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1123 struct sys_reg_desc const *r, bool raz)
1124 {
1125 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1126 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1127 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1128
1129 if (id == SYS_ID_AA64PFR0_EL1) {
1130 if (!vcpu_has_sve(vcpu))
1131 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1132 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
1133 val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT);
1134 val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT);
1135 } else if (id == SYS_ID_AA64PFR1_EL1) {
1136 val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
1137 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
1138 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1139 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1140 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1141 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
1142 } else if (id == SYS_ID_AA64DFR0_EL1) {
1143 /* Limit guests to PMUv3 for ARMv8.1 */
1144 val = cpuid_feature_cap_perfmon_field(val,
1145 ID_AA64DFR0_PMUVER_SHIFT,
1146 ID_AA64DFR0_PMUVER_8_1);
1147 } else if (id == SYS_ID_DFR0_EL1) {
1148 /* Limit guests to PMUv3 for ARMv8.1 */
1149 val = cpuid_feature_cap_perfmon_field(val,
1150 ID_DFR0_PERFMON_SHIFT,
1151 ID_DFR0_PERFMON_8_1);
1152 }
1153
1154 return val;
1155 }
1156
id_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)1157 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1158 const struct sys_reg_desc *r)
1159 {
1160 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1161 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1162
1163 switch (id) {
1164 case SYS_ID_AA64ZFR0_EL1:
1165 if (!vcpu_has_sve(vcpu))
1166 return REG_RAZ;
1167 break;
1168 }
1169
1170 return 0;
1171 }
1172
1173 /* cpufeature ID register access trap handlers */
1174
__access_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r, bool raz)1175 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1176 struct sys_reg_params *p,
1177 const struct sys_reg_desc *r,
1178 bool raz)
1179 {
1180 if (p->is_write)
1181 return write_to_read_only(vcpu, p, r);
1182
1183 p->regval = read_id_reg(vcpu, r, raz);
1184 return true;
1185 }
1186
access_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1187 static bool access_id_reg(struct kvm_vcpu *vcpu,
1188 struct sys_reg_params *p,
1189 const struct sys_reg_desc *r)
1190 {
1191 bool raz = sysreg_visible_as_raz(vcpu, r);
1192
1193 return __access_id_reg(vcpu, p, r, raz);
1194 }
1195
access_raz_id_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1196 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1197 struct sys_reg_params *p,
1198 const struct sys_reg_desc *r)
1199 {
1200 return __access_id_reg(vcpu, p, r, true);
1201 }
1202
1203 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1204 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1205 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1206
1207 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd)1208 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1209 const struct sys_reg_desc *rd)
1210 {
1211 if (vcpu_has_sve(vcpu))
1212 return 0;
1213
1214 return REG_HIDDEN;
1215 }
1216
set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)1217 static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1218 const struct sys_reg_desc *rd,
1219 const struct kvm_one_reg *reg, void __user *uaddr)
1220 {
1221 const u64 id = sys_reg_to_index(rd);
1222 int err;
1223 u64 val;
1224 u8 csv2;
1225
1226 err = reg_from_user(&val, uaddr, id);
1227 if (err)
1228 return err;
1229
1230 /*
1231 * Allow AA64PFR0_EL1.CSV2 to be set from userspace as long as
1232 * it doesn't promise more than what is actually provided (the
1233 * guest could otherwise be covered in ectoplasmic residue).
1234 */
1235 csv2 = cpuid_feature_extract_unsigned_field(val, ID_AA64PFR0_CSV2_SHIFT);
1236 if (csv2 > 1 ||
1237 (csv2 && arm64_get_spectre_v2_state() != SPECTRE_UNAFFECTED))
1238 return -EINVAL;
1239
1240 /* We can only differ with CSV2, and anything else is an error */
1241 val ^= read_id_reg(vcpu, rd, false);
1242 val &= ~(0xFUL << ID_AA64PFR0_CSV2_SHIFT);
1243 if (val)
1244 return -EINVAL;
1245
1246 vcpu->kvm->arch.pfr0_csv2 = csv2;
1247
1248 return 0;
1249 }
1250
1251 /*
1252 * cpufeature ID register user accessors
1253 *
1254 * For now, these registers are immutable for userspace, so no values
1255 * are stored, and for set_id_reg() we don't allow the effective value
1256 * to be changed.
1257 */
__get_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, void __user *uaddr, bool raz)1258 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1259 const struct sys_reg_desc *rd, void __user *uaddr,
1260 bool raz)
1261 {
1262 const u64 id = sys_reg_to_index(rd);
1263 const u64 val = read_id_reg(vcpu, rd, raz);
1264
1265 return reg_to_user(uaddr, &val, id);
1266 }
1267
__set_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, void __user *uaddr, bool raz)1268 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1269 const struct sys_reg_desc *rd, void __user *uaddr,
1270 bool raz)
1271 {
1272 const u64 id = sys_reg_to_index(rd);
1273 int err;
1274 u64 val;
1275
1276 err = reg_from_user(&val, uaddr, id);
1277 if (err)
1278 return err;
1279
1280 /* This is what we mean by invariant: you can't change it. */
1281 if (val != read_id_reg(vcpu, rd, raz))
1282 return -EINVAL;
1283
1284 return 0;
1285 }
1286
get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)1287 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1288 const struct kvm_one_reg *reg, void __user *uaddr)
1289 {
1290 bool raz = sysreg_visible_as_raz(vcpu, rd);
1291
1292 return __get_id_reg(vcpu, rd, uaddr, raz);
1293 }
1294
set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)1295 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1296 const struct kvm_one_reg *reg, void __user *uaddr)
1297 {
1298 bool raz = sysreg_visible_as_raz(vcpu, rd);
1299
1300 return __set_id_reg(vcpu, rd, uaddr, raz);
1301 }
1302
get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)1303 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1304 const struct kvm_one_reg *reg, void __user *uaddr)
1305 {
1306 return __get_id_reg(vcpu, rd, uaddr, true);
1307 }
1308
set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr)1309 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1310 const struct kvm_one_reg *reg, void __user *uaddr)
1311 {
1312 return __set_id_reg(vcpu, rd, uaddr, true);
1313 }
1314
access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1315 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1316 const struct sys_reg_desc *r)
1317 {
1318 if (p->is_write)
1319 return write_to_read_only(vcpu, p, r);
1320
1321 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1322 return true;
1323 }
1324
access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1325 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1326 const struct sys_reg_desc *r)
1327 {
1328 if (p->is_write)
1329 return write_to_read_only(vcpu, p, r);
1330
1331 p->regval = read_sysreg(clidr_el1);
1332 return true;
1333 }
1334
access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1335 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1336 const struct sys_reg_desc *r)
1337 {
1338 int reg = r->reg;
1339
1340 /* See the 32bit mapping in kvm_host.h */
1341 if (p->is_aarch32)
1342 reg = r->reg / 2;
1343
1344 if (p->is_write)
1345 vcpu_write_sys_reg(vcpu, p->regval, reg);
1346 else
1347 p->regval = vcpu_read_sys_reg(vcpu, reg);
1348 return true;
1349 }
1350
access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1351 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1352 const struct sys_reg_desc *r)
1353 {
1354 u32 csselr;
1355
1356 if (p->is_write)
1357 return write_to_read_only(vcpu, p, r);
1358
1359 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1360 p->regval = get_ccsidr(csselr);
1361
1362 /*
1363 * Guests should not be doing cache operations by set/way at all, and
1364 * for this reason, we trap them and attempt to infer the intent, so
1365 * that we can flush the entire guest's address space at the appropriate
1366 * time.
1367 * To prevent this trapping from causing performance problems, let's
1368 * expose the geometry of all data and unified caches (which are
1369 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1370 * [If guests should attempt to infer aliasing properties from the
1371 * geometry (which is not permitted by the architecture), they would
1372 * only do so for virtually indexed caches.]
1373 */
1374 if (!(csselr & 1)) // data or unified cache
1375 p->regval &= ~GENMASK(27, 3);
1376 return true;
1377 }
1378
1379 /* sys_reg_desc initialiser for known cpufeature ID registers */
1380 #define ID_SANITISED(name) { \
1381 SYS_DESC(SYS_##name), \
1382 .access = access_id_reg, \
1383 .get_user = get_id_reg, \
1384 .set_user = set_id_reg, \
1385 .visibility = id_visibility, \
1386 }
1387
1388 /*
1389 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1390 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1391 * (1 <= crm < 8, 0 <= Op2 < 8).
1392 */
1393 #define ID_UNALLOCATED(crm, op2) { \
1394 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1395 .access = access_raz_id_reg, \
1396 .get_user = get_raz_id_reg, \
1397 .set_user = set_raz_id_reg, \
1398 }
1399
1400 /*
1401 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1402 * For now, these are exposed just like unallocated ID regs: they appear
1403 * RAZ for the guest.
1404 */
1405 #define ID_HIDDEN(name) { \
1406 SYS_DESC(SYS_##name), \
1407 .access = access_raz_id_reg, \
1408 .get_user = get_raz_id_reg, \
1409 .set_user = set_raz_id_reg, \
1410 }
1411
1412 /*
1413 * Architected system registers.
1414 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1415 *
1416 * Debug handling: We do trap most, if not all debug related system
1417 * registers. The implementation is good enough to ensure that a guest
1418 * can use these with minimal performance degradation. The drawback is
1419 * that we don't implement any of the external debug, none of the
1420 * OSlock protocol. This should be revisited if we ever encounter a
1421 * more demanding guest...
1422 */
1423 static const struct sys_reg_desc sys_reg_descs[] = {
1424 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1425 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1426 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1427
1428 DBG_BCR_BVR_WCR_WVR_EL1(0),
1429 DBG_BCR_BVR_WCR_WVR_EL1(1),
1430 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1431 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1432 DBG_BCR_BVR_WCR_WVR_EL1(2),
1433 DBG_BCR_BVR_WCR_WVR_EL1(3),
1434 DBG_BCR_BVR_WCR_WVR_EL1(4),
1435 DBG_BCR_BVR_WCR_WVR_EL1(5),
1436 DBG_BCR_BVR_WCR_WVR_EL1(6),
1437 DBG_BCR_BVR_WCR_WVR_EL1(7),
1438 DBG_BCR_BVR_WCR_WVR_EL1(8),
1439 DBG_BCR_BVR_WCR_WVR_EL1(9),
1440 DBG_BCR_BVR_WCR_WVR_EL1(10),
1441 DBG_BCR_BVR_WCR_WVR_EL1(11),
1442 DBG_BCR_BVR_WCR_WVR_EL1(12),
1443 DBG_BCR_BVR_WCR_WVR_EL1(13),
1444 DBG_BCR_BVR_WCR_WVR_EL1(14),
1445 DBG_BCR_BVR_WCR_WVR_EL1(15),
1446
1447 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1448 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1449 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1450 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1451 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1452 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1453 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1454 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1455
1456 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1457 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1458 // DBGDTR[TR]X_EL0 share the same encoding
1459 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1460
1461 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1462
1463 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1464
1465 /*
1466 * ID regs: all ID_SANITISED() entries here must have corresponding
1467 * entries in arm64_ftr_regs[].
1468 */
1469
1470 /* AArch64 mappings of the AArch32 ID registers */
1471 /* CRm=1 */
1472 ID_SANITISED(ID_PFR0_EL1),
1473 ID_SANITISED(ID_PFR1_EL1),
1474 ID_SANITISED(ID_DFR0_EL1),
1475 ID_HIDDEN(ID_AFR0_EL1),
1476 ID_SANITISED(ID_MMFR0_EL1),
1477 ID_SANITISED(ID_MMFR1_EL1),
1478 ID_SANITISED(ID_MMFR2_EL1),
1479 ID_SANITISED(ID_MMFR3_EL1),
1480
1481 /* CRm=2 */
1482 ID_SANITISED(ID_ISAR0_EL1),
1483 ID_SANITISED(ID_ISAR1_EL1),
1484 ID_SANITISED(ID_ISAR2_EL1),
1485 ID_SANITISED(ID_ISAR3_EL1),
1486 ID_SANITISED(ID_ISAR4_EL1),
1487 ID_SANITISED(ID_ISAR5_EL1),
1488 ID_SANITISED(ID_MMFR4_EL1),
1489 ID_SANITISED(ID_ISAR6_EL1),
1490
1491 /* CRm=3 */
1492 ID_SANITISED(MVFR0_EL1),
1493 ID_SANITISED(MVFR1_EL1),
1494 ID_SANITISED(MVFR2_EL1),
1495 ID_UNALLOCATED(3,3),
1496 ID_SANITISED(ID_PFR2_EL1),
1497 ID_HIDDEN(ID_DFR1_EL1),
1498 ID_SANITISED(ID_MMFR5_EL1),
1499 ID_UNALLOCATED(3,7),
1500
1501 /* AArch64 ID registers */
1502 /* CRm=4 */
1503 { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg,
1504 .get_user = get_id_reg, .set_user = set_id_aa64pfr0_el1, },
1505 ID_SANITISED(ID_AA64PFR1_EL1),
1506 ID_UNALLOCATED(4,2),
1507 ID_UNALLOCATED(4,3),
1508 ID_SANITISED(ID_AA64ZFR0_EL1),
1509 ID_UNALLOCATED(4,5),
1510 ID_UNALLOCATED(4,6),
1511 ID_UNALLOCATED(4,7),
1512
1513 /* CRm=5 */
1514 ID_SANITISED(ID_AA64DFR0_EL1),
1515 ID_SANITISED(ID_AA64DFR1_EL1),
1516 ID_UNALLOCATED(5,2),
1517 ID_UNALLOCATED(5,3),
1518 ID_HIDDEN(ID_AA64AFR0_EL1),
1519 ID_HIDDEN(ID_AA64AFR1_EL1),
1520 ID_UNALLOCATED(5,6),
1521 ID_UNALLOCATED(5,7),
1522
1523 /* CRm=6 */
1524 ID_SANITISED(ID_AA64ISAR0_EL1),
1525 ID_SANITISED(ID_AA64ISAR1_EL1),
1526 ID_SANITISED(ID_AA64ISAR2_EL1),
1527 ID_UNALLOCATED(6,3),
1528 ID_UNALLOCATED(6,4),
1529 ID_UNALLOCATED(6,5),
1530 ID_UNALLOCATED(6,6),
1531 ID_UNALLOCATED(6,7),
1532
1533 /* CRm=7 */
1534 ID_SANITISED(ID_AA64MMFR0_EL1),
1535 ID_SANITISED(ID_AA64MMFR1_EL1),
1536 ID_SANITISED(ID_AA64MMFR2_EL1),
1537 ID_UNALLOCATED(7,3),
1538 ID_UNALLOCATED(7,4),
1539 ID_UNALLOCATED(7,5),
1540 ID_UNALLOCATED(7,6),
1541 ID_UNALLOCATED(7,7),
1542
1543 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1544 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
1545 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1546
1547 { SYS_DESC(SYS_RGSR_EL1), undef_access },
1548 { SYS_DESC(SYS_GCR_EL1), undef_access },
1549
1550 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1551 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1552 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1553 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1554
1555 PTRAUTH_KEY(APIA),
1556 PTRAUTH_KEY(APIB),
1557 PTRAUTH_KEY(APDA),
1558 PTRAUTH_KEY(APDB),
1559 PTRAUTH_KEY(APGA),
1560
1561 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1562 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1563 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1564
1565 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1566 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1567 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1568 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1569 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1570 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1571 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1572 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1573
1574 { SYS_DESC(SYS_TFSR_EL1), undef_access },
1575 { SYS_DESC(SYS_TFSRE0_EL1), undef_access },
1576
1577 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1578 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1579
1580 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1581 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1582
1583 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1584 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1585
1586 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1587 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1588 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1589 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1590 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1591
1592 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1593 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1594
1595 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1596 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1597 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1598 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1599 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1600 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1601 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1602 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1603 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1604 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1605 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1606 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1607
1608 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1609 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1610
1611 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
1612
1613 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1614
1615 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1616 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1617 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1618 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1619
1620 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
1621 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1622 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1623 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1624 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1625 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1626 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1627 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1628 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1629 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1630 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1631 /*
1632 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1633 * in 32bit mode. Here we choose to reset it as zero for consistency.
1634 */
1635 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1636 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1637
1638 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1639 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1640
1641 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
1642
1643 { SYS_DESC(SYS_AMCR_EL0), undef_access },
1644 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
1645 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
1646 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
1647 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
1648 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
1649 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
1650 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
1651 AMU_AMEVCNTR0_EL0(0),
1652 AMU_AMEVCNTR0_EL0(1),
1653 AMU_AMEVCNTR0_EL0(2),
1654 AMU_AMEVCNTR0_EL0(3),
1655 AMU_AMEVCNTR0_EL0(4),
1656 AMU_AMEVCNTR0_EL0(5),
1657 AMU_AMEVCNTR0_EL0(6),
1658 AMU_AMEVCNTR0_EL0(7),
1659 AMU_AMEVCNTR0_EL0(8),
1660 AMU_AMEVCNTR0_EL0(9),
1661 AMU_AMEVCNTR0_EL0(10),
1662 AMU_AMEVCNTR0_EL0(11),
1663 AMU_AMEVCNTR0_EL0(12),
1664 AMU_AMEVCNTR0_EL0(13),
1665 AMU_AMEVCNTR0_EL0(14),
1666 AMU_AMEVCNTR0_EL0(15),
1667 AMU_AMEVTYPER0_EL0(0),
1668 AMU_AMEVTYPER0_EL0(1),
1669 AMU_AMEVTYPER0_EL0(2),
1670 AMU_AMEVTYPER0_EL0(3),
1671 AMU_AMEVTYPER0_EL0(4),
1672 AMU_AMEVTYPER0_EL0(5),
1673 AMU_AMEVTYPER0_EL0(6),
1674 AMU_AMEVTYPER0_EL0(7),
1675 AMU_AMEVTYPER0_EL0(8),
1676 AMU_AMEVTYPER0_EL0(9),
1677 AMU_AMEVTYPER0_EL0(10),
1678 AMU_AMEVTYPER0_EL0(11),
1679 AMU_AMEVTYPER0_EL0(12),
1680 AMU_AMEVTYPER0_EL0(13),
1681 AMU_AMEVTYPER0_EL0(14),
1682 AMU_AMEVTYPER0_EL0(15),
1683 AMU_AMEVCNTR1_EL0(0),
1684 AMU_AMEVCNTR1_EL0(1),
1685 AMU_AMEVCNTR1_EL0(2),
1686 AMU_AMEVCNTR1_EL0(3),
1687 AMU_AMEVCNTR1_EL0(4),
1688 AMU_AMEVCNTR1_EL0(5),
1689 AMU_AMEVCNTR1_EL0(6),
1690 AMU_AMEVCNTR1_EL0(7),
1691 AMU_AMEVCNTR1_EL0(8),
1692 AMU_AMEVCNTR1_EL0(9),
1693 AMU_AMEVCNTR1_EL0(10),
1694 AMU_AMEVCNTR1_EL0(11),
1695 AMU_AMEVCNTR1_EL0(12),
1696 AMU_AMEVCNTR1_EL0(13),
1697 AMU_AMEVCNTR1_EL0(14),
1698 AMU_AMEVCNTR1_EL0(15),
1699 AMU_AMEVTYPER1_EL0(0),
1700 AMU_AMEVTYPER1_EL0(1),
1701 AMU_AMEVTYPER1_EL0(2),
1702 AMU_AMEVTYPER1_EL0(3),
1703 AMU_AMEVTYPER1_EL0(4),
1704 AMU_AMEVTYPER1_EL0(5),
1705 AMU_AMEVTYPER1_EL0(6),
1706 AMU_AMEVTYPER1_EL0(7),
1707 AMU_AMEVTYPER1_EL0(8),
1708 AMU_AMEVTYPER1_EL0(9),
1709 AMU_AMEVTYPER1_EL0(10),
1710 AMU_AMEVTYPER1_EL0(11),
1711 AMU_AMEVTYPER1_EL0(12),
1712 AMU_AMEVTYPER1_EL0(13),
1713 AMU_AMEVTYPER1_EL0(14),
1714 AMU_AMEVTYPER1_EL0(15),
1715
1716 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1717 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1718 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1719
1720 /* PMEVCNTRn_EL0 */
1721 PMU_PMEVCNTR_EL0(0),
1722 PMU_PMEVCNTR_EL0(1),
1723 PMU_PMEVCNTR_EL0(2),
1724 PMU_PMEVCNTR_EL0(3),
1725 PMU_PMEVCNTR_EL0(4),
1726 PMU_PMEVCNTR_EL0(5),
1727 PMU_PMEVCNTR_EL0(6),
1728 PMU_PMEVCNTR_EL0(7),
1729 PMU_PMEVCNTR_EL0(8),
1730 PMU_PMEVCNTR_EL0(9),
1731 PMU_PMEVCNTR_EL0(10),
1732 PMU_PMEVCNTR_EL0(11),
1733 PMU_PMEVCNTR_EL0(12),
1734 PMU_PMEVCNTR_EL0(13),
1735 PMU_PMEVCNTR_EL0(14),
1736 PMU_PMEVCNTR_EL0(15),
1737 PMU_PMEVCNTR_EL0(16),
1738 PMU_PMEVCNTR_EL0(17),
1739 PMU_PMEVCNTR_EL0(18),
1740 PMU_PMEVCNTR_EL0(19),
1741 PMU_PMEVCNTR_EL0(20),
1742 PMU_PMEVCNTR_EL0(21),
1743 PMU_PMEVCNTR_EL0(22),
1744 PMU_PMEVCNTR_EL0(23),
1745 PMU_PMEVCNTR_EL0(24),
1746 PMU_PMEVCNTR_EL0(25),
1747 PMU_PMEVCNTR_EL0(26),
1748 PMU_PMEVCNTR_EL0(27),
1749 PMU_PMEVCNTR_EL0(28),
1750 PMU_PMEVCNTR_EL0(29),
1751 PMU_PMEVCNTR_EL0(30),
1752 /* PMEVTYPERn_EL0 */
1753 PMU_PMEVTYPER_EL0(0),
1754 PMU_PMEVTYPER_EL0(1),
1755 PMU_PMEVTYPER_EL0(2),
1756 PMU_PMEVTYPER_EL0(3),
1757 PMU_PMEVTYPER_EL0(4),
1758 PMU_PMEVTYPER_EL0(5),
1759 PMU_PMEVTYPER_EL0(6),
1760 PMU_PMEVTYPER_EL0(7),
1761 PMU_PMEVTYPER_EL0(8),
1762 PMU_PMEVTYPER_EL0(9),
1763 PMU_PMEVTYPER_EL0(10),
1764 PMU_PMEVTYPER_EL0(11),
1765 PMU_PMEVTYPER_EL0(12),
1766 PMU_PMEVTYPER_EL0(13),
1767 PMU_PMEVTYPER_EL0(14),
1768 PMU_PMEVTYPER_EL0(15),
1769 PMU_PMEVTYPER_EL0(16),
1770 PMU_PMEVTYPER_EL0(17),
1771 PMU_PMEVTYPER_EL0(18),
1772 PMU_PMEVTYPER_EL0(19),
1773 PMU_PMEVTYPER_EL0(20),
1774 PMU_PMEVTYPER_EL0(21),
1775 PMU_PMEVTYPER_EL0(22),
1776 PMU_PMEVTYPER_EL0(23),
1777 PMU_PMEVTYPER_EL0(24),
1778 PMU_PMEVTYPER_EL0(25),
1779 PMU_PMEVTYPER_EL0(26),
1780 PMU_PMEVTYPER_EL0(27),
1781 PMU_PMEVTYPER_EL0(28),
1782 PMU_PMEVTYPER_EL0(29),
1783 PMU_PMEVTYPER_EL0(30),
1784 /*
1785 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1786 * in 32bit mode. Here we choose to reset it as zero for consistency.
1787 */
1788 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1789
1790 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1791 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1792 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1793 };
1794
trap_dbgidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1795 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1796 struct sys_reg_params *p,
1797 const struct sys_reg_desc *r)
1798 {
1799 if (p->is_write) {
1800 return ignore_write(vcpu, p);
1801 } else {
1802 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1803 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1804 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1805
1806 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1807 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1808 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1809 | (6 << 16) | (el3 << 14) | (el3 << 12));
1810 return true;
1811 }
1812 }
1813
trap_debug32(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r)1814 static bool trap_debug32(struct kvm_vcpu *vcpu,
1815 struct sys_reg_params *p,
1816 const struct sys_reg_desc *r)
1817 {
1818 if (p->is_write) {
1819 vcpu_cp14(vcpu, r->reg) = p->regval;
1820 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1821 } else {
1822 p->regval = vcpu_cp14(vcpu, r->reg);
1823 }
1824
1825 return true;
1826 }
1827
1828 /* AArch32 debug register mappings
1829 *
1830 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1831 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1832 *
1833 * All control registers and watchpoint value registers are mapped to
1834 * the lower 32 bits of their AArch64 equivalents. We share the trap
1835 * handlers with the above AArch64 code which checks what mode the
1836 * system is in.
1837 */
1838
trap_xvr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *rd)1839 static bool trap_xvr(struct kvm_vcpu *vcpu,
1840 struct sys_reg_params *p,
1841 const struct sys_reg_desc *rd)
1842 {
1843 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1844
1845 if (p->is_write) {
1846 u64 val = *dbg_reg;
1847
1848 val &= 0xffffffffUL;
1849 val |= p->regval << 32;
1850 *dbg_reg = val;
1851
1852 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1853 } else {
1854 p->regval = *dbg_reg >> 32;
1855 }
1856
1857 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1858
1859 return true;
1860 }
1861
1862 #define DBG_BCR_BVR_WCR_WVR(n) \
1863 /* DBGBVRn */ \
1864 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1865 /* DBGBCRn */ \
1866 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1867 /* DBGWVRn */ \
1868 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1869 /* DBGWCRn */ \
1870 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1871
1872 #define DBGBXVR(n) \
1873 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1874
1875 /*
1876 * Trapped cp14 registers. We generally ignore most of the external
1877 * debug, on the principle that they don't really make sense to a
1878 * guest. Revisit this one day, would this principle change.
1879 */
1880 static const struct sys_reg_desc cp14_regs[] = {
1881 /* DBGIDR */
1882 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1883 /* DBGDTRRXext */
1884 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1885
1886 DBG_BCR_BVR_WCR_WVR(0),
1887 /* DBGDSCRint */
1888 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1889 DBG_BCR_BVR_WCR_WVR(1),
1890 /* DBGDCCINT */
1891 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
1892 /* DBGDSCRext */
1893 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
1894 DBG_BCR_BVR_WCR_WVR(2),
1895 /* DBGDTR[RT]Xint */
1896 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1897 /* DBGDTR[RT]Xext */
1898 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1899 DBG_BCR_BVR_WCR_WVR(3),
1900 DBG_BCR_BVR_WCR_WVR(4),
1901 DBG_BCR_BVR_WCR_WVR(5),
1902 /* DBGWFAR */
1903 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1904 /* DBGOSECCR */
1905 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1906 DBG_BCR_BVR_WCR_WVR(6),
1907 /* DBGVCR */
1908 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
1909 DBG_BCR_BVR_WCR_WVR(7),
1910 DBG_BCR_BVR_WCR_WVR(8),
1911 DBG_BCR_BVR_WCR_WVR(9),
1912 DBG_BCR_BVR_WCR_WVR(10),
1913 DBG_BCR_BVR_WCR_WVR(11),
1914 DBG_BCR_BVR_WCR_WVR(12),
1915 DBG_BCR_BVR_WCR_WVR(13),
1916 DBG_BCR_BVR_WCR_WVR(14),
1917 DBG_BCR_BVR_WCR_WVR(15),
1918
1919 /* DBGDRAR (32bit) */
1920 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1921
1922 DBGBXVR(0),
1923 /* DBGOSLAR */
1924 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1925 DBGBXVR(1),
1926 /* DBGOSLSR */
1927 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1928 DBGBXVR(2),
1929 DBGBXVR(3),
1930 /* DBGOSDLR */
1931 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1932 DBGBXVR(4),
1933 /* DBGPRCR */
1934 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1935 DBGBXVR(5),
1936 DBGBXVR(6),
1937 DBGBXVR(7),
1938 DBGBXVR(8),
1939 DBGBXVR(9),
1940 DBGBXVR(10),
1941 DBGBXVR(11),
1942 DBGBXVR(12),
1943 DBGBXVR(13),
1944 DBGBXVR(14),
1945 DBGBXVR(15),
1946
1947 /* DBGDSAR (32bit) */
1948 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1949
1950 /* DBGDEVID2 */
1951 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1952 /* DBGDEVID1 */
1953 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1954 /* DBGDEVID */
1955 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1956 /* DBGCLAIMSET */
1957 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1958 /* DBGCLAIMCLR */
1959 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1960 /* DBGAUTHSTATUS */
1961 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1962 };
1963
1964 /* Trapped cp14 64bit registers */
1965 static const struct sys_reg_desc cp14_64_regs[] = {
1966 /* DBGDRAR (64bit) */
1967 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1968
1969 /* DBGDSAR (64bit) */
1970 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1971 };
1972
1973 /* Macro to expand the PMEVCNTRn register */
1974 #define PMU_PMEVCNTR(n) \
1975 /* PMEVCNTRn */ \
1976 { Op1(0), CRn(0b1110), \
1977 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1978 access_pmu_evcntr }
1979
1980 /* Macro to expand the PMEVTYPERn register */
1981 #define PMU_PMEVTYPER(n) \
1982 /* PMEVTYPERn */ \
1983 { Op1(0), CRn(0b1110), \
1984 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1985 access_pmu_evtyper }
1986
1987 /*
1988 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1989 * depending on the way they are accessed (as a 32bit or a 64bit
1990 * register).
1991 */
1992 static const struct sys_reg_desc cp15_regs[] = {
1993 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1994 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1995 { Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr },
1996 { Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr },
1997 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1998 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1999 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
2000 { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
2001 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
2002 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
2003 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
2004 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
2005 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
2006 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
2007 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
2008
2009 /*
2010 * DC{C,I,CI}SW operations:
2011 */
2012 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2013 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2014 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2015
2016 /* PMU */
2017 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
2018 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
2019 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
2020 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
2021 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
2022 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
2023 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
2024 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
2025 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
2026 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
2027 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
2028 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
2029 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
2030 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
2031 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
2032
2033 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
2034 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
2035 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
2036 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
2037
2038 /* ICC_SRE */
2039 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2040
2041 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
2042
2043 /* Arch Tmers */
2044 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2045 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2046
2047 /* PMEVCNTRn */
2048 PMU_PMEVCNTR(0),
2049 PMU_PMEVCNTR(1),
2050 PMU_PMEVCNTR(2),
2051 PMU_PMEVCNTR(3),
2052 PMU_PMEVCNTR(4),
2053 PMU_PMEVCNTR(5),
2054 PMU_PMEVCNTR(6),
2055 PMU_PMEVCNTR(7),
2056 PMU_PMEVCNTR(8),
2057 PMU_PMEVCNTR(9),
2058 PMU_PMEVCNTR(10),
2059 PMU_PMEVCNTR(11),
2060 PMU_PMEVCNTR(12),
2061 PMU_PMEVCNTR(13),
2062 PMU_PMEVCNTR(14),
2063 PMU_PMEVCNTR(15),
2064 PMU_PMEVCNTR(16),
2065 PMU_PMEVCNTR(17),
2066 PMU_PMEVCNTR(18),
2067 PMU_PMEVCNTR(19),
2068 PMU_PMEVCNTR(20),
2069 PMU_PMEVCNTR(21),
2070 PMU_PMEVCNTR(22),
2071 PMU_PMEVCNTR(23),
2072 PMU_PMEVCNTR(24),
2073 PMU_PMEVCNTR(25),
2074 PMU_PMEVCNTR(26),
2075 PMU_PMEVCNTR(27),
2076 PMU_PMEVCNTR(28),
2077 PMU_PMEVCNTR(29),
2078 PMU_PMEVCNTR(30),
2079 /* PMEVTYPERn */
2080 PMU_PMEVTYPER(0),
2081 PMU_PMEVTYPER(1),
2082 PMU_PMEVTYPER(2),
2083 PMU_PMEVTYPER(3),
2084 PMU_PMEVTYPER(4),
2085 PMU_PMEVTYPER(5),
2086 PMU_PMEVTYPER(6),
2087 PMU_PMEVTYPER(7),
2088 PMU_PMEVTYPER(8),
2089 PMU_PMEVTYPER(9),
2090 PMU_PMEVTYPER(10),
2091 PMU_PMEVTYPER(11),
2092 PMU_PMEVTYPER(12),
2093 PMU_PMEVTYPER(13),
2094 PMU_PMEVTYPER(14),
2095 PMU_PMEVTYPER(15),
2096 PMU_PMEVTYPER(16),
2097 PMU_PMEVTYPER(17),
2098 PMU_PMEVTYPER(18),
2099 PMU_PMEVTYPER(19),
2100 PMU_PMEVTYPER(20),
2101 PMU_PMEVTYPER(21),
2102 PMU_PMEVTYPER(22),
2103 PMU_PMEVTYPER(23),
2104 PMU_PMEVTYPER(24),
2105 PMU_PMEVTYPER(25),
2106 PMU_PMEVTYPER(26),
2107 PMU_PMEVTYPER(27),
2108 PMU_PMEVTYPER(28),
2109 PMU_PMEVTYPER(29),
2110 PMU_PMEVTYPER(30),
2111 /* PMCCFILTR */
2112 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2113
2114 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2115 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2116 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
2117 };
2118
2119 static const struct sys_reg_desc cp15_64_regs[] = {
2120 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
2121 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2122 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2123 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
2124 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2125 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2126 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2127 };
2128
check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, bool is_32)2129 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2130 bool is_32)
2131 {
2132 unsigned int i;
2133
2134 for (i = 0; i < n; i++) {
2135 if (!is_32 && table[i].reg && !table[i].reset) {
2136 kvm_err("sys_reg table %p entry %d has lacks reset\n",
2137 table, i);
2138 return 1;
2139 }
2140
2141 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2142 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2143 return 1;
2144 }
2145 }
2146
2147 return 0;
2148 }
2149
match_sys_reg(const void *key, const void *elt)2150 static int match_sys_reg(const void *key, const void *elt)
2151 {
2152 const unsigned long pval = (unsigned long)key;
2153 const struct sys_reg_desc *r = elt;
2154
2155 return pval - reg_to_encoding(r);
2156 }
2157
find_reg(const struct sys_reg_params *params, const struct sys_reg_desc table[], unsigned int num)2158 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2159 const struct sys_reg_desc table[],
2160 unsigned int num)
2161 {
2162 unsigned long pval = reg_to_encoding(params);
2163
2164 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
2165 }
2166
kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)2167 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2168 {
2169 kvm_inject_undefined(vcpu);
2170 return 1;
2171 }
2172
perform_access(struct kvm_vcpu *vcpu, struct sys_reg_params *params, const struct sys_reg_desc *r)2173 static void perform_access(struct kvm_vcpu *vcpu,
2174 struct sys_reg_params *params,
2175 const struct sys_reg_desc *r)
2176 {
2177 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2178
2179 /* Check for regs disabled by runtime config */
2180 if (sysreg_hidden(vcpu, r)) {
2181 kvm_inject_undefined(vcpu);
2182 return;
2183 }
2184
2185 /*
2186 * Not having an accessor means that we have configured a trap
2187 * that we don't know how to handle. This certainly qualifies
2188 * as a gross bug that should be fixed right away.
2189 */
2190 BUG_ON(!r->access);
2191
2192 /* Skip instruction if instructed so */
2193 if (likely(r->access(vcpu, params, r)))
2194 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
2195 }
2196
2197 /*
2198 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2199 * call the corresponding trap handler.
2200 *
2201 * @params: pointer to the descriptor of the access
2202 * @table: array of trap descriptors
2203 * @num: size of the trap descriptor array
2204 *
2205 * Return 0 if the access has been handled, and -1 if not.
2206 */
emulate_cp(struct kvm_vcpu *vcpu, struct sys_reg_params *params, const struct sys_reg_desc *table, size_t num)2207 static int emulate_cp(struct kvm_vcpu *vcpu,
2208 struct sys_reg_params *params,
2209 const struct sys_reg_desc *table,
2210 size_t num)
2211 {
2212 const struct sys_reg_desc *r;
2213
2214 if (!table)
2215 return -1; /* Not handled */
2216
2217 r = find_reg(params, table, num);
2218
2219 if (r) {
2220 perform_access(vcpu, params, r);
2221 return 0;
2222 }
2223
2224 /* Not handled */
2225 return -1;
2226 }
2227
unhandled_cp_access(struct kvm_vcpu *vcpu, struct sys_reg_params *params)2228 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2229 struct sys_reg_params *params)
2230 {
2231 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2232 int cp = -1;
2233
2234 switch (esr_ec) {
2235 case ESR_ELx_EC_CP15_32:
2236 case ESR_ELx_EC_CP15_64:
2237 cp = 15;
2238 break;
2239 case ESR_ELx_EC_CP14_MR:
2240 case ESR_ELx_EC_CP14_64:
2241 cp = 14;
2242 break;
2243 default:
2244 WARN_ON(1);
2245 }
2246
2247 print_sys_reg_msg(params,
2248 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2249 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2250 kvm_inject_undefined(vcpu);
2251 }
2252
2253 /**
2254 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2255 * @vcpu: The VCPU pointer
2256 * @run: The kvm_run struct
2257 */
kvm_handle_cp_64(struct kvm_vcpu *vcpu, const struct sys_reg_desc *global, size_t nr_global)2258 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2259 const struct sys_reg_desc *global,
2260 size_t nr_global)
2261 {
2262 struct sys_reg_params params;
2263 u32 esr = kvm_vcpu_get_esr(vcpu);
2264 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2265 int Rt2 = (esr >> 10) & 0x1f;
2266
2267 params.is_aarch32 = true;
2268 params.is_32bit = false;
2269 params.CRm = (esr >> 1) & 0xf;
2270 params.is_write = ((esr & 1) == 0);
2271
2272 params.Op0 = 0;
2273 params.Op1 = (esr >> 16) & 0xf;
2274 params.Op2 = 0;
2275 params.CRn = 0;
2276
2277 /*
2278 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2279 * backends between AArch32 and AArch64, we get away with it.
2280 */
2281 if (params.is_write) {
2282 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2283 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2284 }
2285
2286 /*
2287 * If the table contains a handler, handle the
2288 * potential register operation in the case of a read and return
2289 * with success.
2290 */
2291 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2292 /* Split up the value between registers for the read side */
2293 if (!params.is_write) {
2294 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2295 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2296 }
2297
2298 return 1;
2299 }
2300
2301 unhandled_cp_access(vcpu, ¶ms);
2302 return 1;
2303 }
2304
2305 /**
2306 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2307 * @vcpu: The VCPU pointer
2308 * @run: The kvm_run struct
2309 */
kvm_handle_cp_32(struct kvm_vcpu *vcpu, const struct sys_reg_desc *global, size_t nr_global)2310 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2311 const struct sys_reg_desc *global,
2312 size_t nr_global)
2313 {
2314 struct sys_reg_params params;
2315 u32 esr = kvm_vcpu_get_esr(vcpu);
2316 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2317
2318 params.is_aarch32 = true;
2319 params.is_32bit = true;
2320 params.CRm = (esr >> 1) & 0xf;
2321 params.regval = vcpu_get_reg(vcpu, Rt);
2322 params.is_write = ((esr & 1) == 0);
2323 params.CRn = (esr >> 10) & 0xf;
2324 params.Op0 = 0;
2325 params.Op1 = (esr >> 14) & 0x7;
2326 params.Op2 = (esr >> 17) & 0x7;
2327
2328 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) {
2329 if (!params.is_write)
2330 vcpu_set_reg(vcpu, Rt, params.regval);
2331 return 1;
2332 }
2333
2334 unhandled_cp_access(vcpu, ¶ms);
2335 return 1;
2336 }
2337
kvm_handle_cp15_64(struct kvm_vcpu *vcpu)2338 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
2339 {
2340 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
2341 }
2342
kvm_handle_cp15_32(struct kvm_vcpu *vcpu)2343 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
2344 {
2345 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
2346 }
2347
kvm_handle_cp14_64(struct kvm_vcpu *vcpu)2348 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
2349 {
2350 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
2351 }
2352
kvm_handle_cp14_32(struct kvm_vcpu *vcpu)2353 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
2354 {
2355 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs));
2356 }
2357
is_imp_def_sys_reg(struct sys_reg_params *params)2358 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
2359 {
2360 // See ARM DDI 0487E.a, section D12.3.2
2361 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
2362 }
2363
emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params)2364 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2365 struct sys_reg_params *params)
2366 {
2367 const struct sys_reg_desc *r;
2368
2369 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2370
2371 if (likely(r)) {
2372 perform_access(vcpu, params, r);
2373 } else if (is_imp_def_sys_reg(params)) {
2374 kvm_inject_undefined(vcpu);
2375 } else {
2376 print_sys_reg_msg(params,
2377 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
2378 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2379 kvm_inject_undefined(vcpu);
2380 }
2381 return 1;
2382 }
2383
2384 /**
2385 * kvm_reset_sys_regs - sets system registers to reset value
2386 * @vcpu: The VCPU pointer
2387 *
2388 * This function finds the right table above and sets the registers on the
2389 * virtual CPU struct to their architecturally defined reset values.
2390 */
kvm_reset_sys_regs(struct kvm_vcpu *vcpu)2391 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2392 {
2393 unsigned long i;
2394
2395 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++)
2396 if (sys_reg_descs[i].reset)
2397 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]);
2398 }
2399
2400 /**
2401 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2402 * @vcpu: The VCPU pointer
2403 */
kvm_handle_sys_reg(struct kvm_vcpu *vcpu)2404 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
2405 {
2406 struct sys_reg_params params;
2407 unsigned long esr = kvm_vcpu_get_esr(vcpu);
2408 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2409 int ret;
2410
2411 trace_kvm_handle_sys_reg(esr);
2412
2413 params.is_aarch32 = false;
2414 params.is_32bit = false;
2415 params.Op0 = (esr >> 20) & 3;
2416 params.Op1 = (esr >> 14) & 0x7;
2417 params.CRn = (esr >> 10) & 0xf;
2418 params.CRm = (esr >> 1) & 0xf;
2419 params.Op2 = (esr >> 17) & 0x7;
2420 params.regval = vcpu_get_reg(vcpu, Rt);
2421 params.is_write = !(esr & 1);
2422
2423 ret = emulate_sys_reg(vcpu, ¶ms);
2424
2425 if (!params.is_write)
2426 vcpu_set_reg(vcpu, Rt, params.regval);
2427 return ret;
2428 }
2429
2430 /******************************************************************************
2431 * Userspace API
2432 *****************************************************************************/
2433
index_to_params(u64 id, struct sys_reg_params *params)2434 static bool index_to_params(u64 id, struct sys_reg_params *params)
2435 {
2436 switch (id & KVM_REG_SIZE_MASK) {
2437 case KVM_REG_SIZE_U64:
2438 /* Any unused index bits means it's not valid. */
2439 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2440 | KVM_REG_ARM_COPROC_MASK
2441 | KVM_REG_ARM64_SYSREG_OP0_MASK
2442 | KVM_REG_ARM64_SYSREG_OP1_MASK
2443 | KVM_REG_ARM64_SYSREG_CRN_MASK
2444 | KVM_REG_ARM64_SYSREG_CRM_MASK
2445 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2446 return false;
2447 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2448 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2449 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2450 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2451 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2452 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2453 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2454 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2455 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2456 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2457 return true;
2458 default:
2459 return false;
2460 }
2461 }
2462
find_reg_by_id(u64 id, struct sys_reg_params *params, const struct sys_reg_desc table[], unsigned int num)2463 const struct sys_reg_desc *find_reg_by_id(u64 id,
2464 struct sys_reg_params *params,
2465 const struct sys_reg_desc table[],
2466 unsigned int num)
2467 {
2468 if (!index_to_params(id, params))
2469 return NULL;
2470
2471 return find_reg(params, table, num);
2472 }
2473
2474 /* Decode an index value, and find the sys_reg_desc entry. */
index_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id)2475 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2476 u64 id)
2477 {
2478 const struct sys_reg_desc *r;
2479 struct sys_reg_params params;
2480
2481 /* We only do sys_reg for now. */
2482 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2483 return NULL;
2484
2485 if (!index_to_params(id, ¶ms))
2486 return NULL;
2487
2488 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2489
2490 /* Not saved in the sys_reg array and not otherwise accessible? */
2491 if (r && !(r->reg || r->get_user))
2492 r = NULL;
2493
2494 return r;
2495 }
2496
2497 /*
2498 * These are the invariant sys_reg registers: we let the guest see the
2499 * host versions of these, so they're part of the guest state.
2500 *
2501 * A future CPU may provide a mechanism to present different values to
2502 * the guest, or a future kvm may trap them.
2503 */
2504
2505 #define FUNCTION_INVARIANT(reg) \
2506 static void get_##reg(struct kvm_vcpu *v, \
2507 const struct sys_reg_desc *r) \
2508 { \
2509 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2510 }
2511
2512 FUNCTION_INVARIANT(midr_el1)
2513 FUNCTION_INVARIANT(revidr_el1)
2514 FUNCTION_INVARIANT(clidr_el1)
2515 FUNCTION_INVARIANT(aidr_el1)
2516
get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)2517 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2518 {
2519 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2520 }
2521
2522 /* ->val is filled in by kvm_sys_reg_table_init() */
2523 static struct sys_reg_desc invariant_sys_regs[] = {
2524 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2525 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2526 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2527 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2528 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2529 };
2530
reg_from_user(u64 *val, const void __user *uaddr, u64 id)2531 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2532 {
2533 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2534 return -EFAULT;
2535 return 0;
2536 }
2537
reg_to_user(void __user *uaddr, const u64 *val, u64 id)2538 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2539 {
2540 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2541 return -EFAULT;
2542 return 0;
2543 }
2544
get_invariant_sys_reg(u64 id, void __user *uaddr)2545 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2546 {
2547 struct sys_reg_params params;
2548 const struct sys_reg_desc *r;
2549
2550 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2551 ARRAY_SIZE(invariant_sys_regs));
2552 if (!r)
2553 return -ENOENT;
2554
2555 return reg_to_user(uaddr, &r->val, id);
2556 }
2557
set_invariant_sys_reg(u64 id, void __user *uaddr)2558 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2559 {
2560 struct sys_reg_params params;
2561 const struct sys_reg_desc *r;
2562 int err;
2563 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2564
2565 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2566 ARRAY_SIZE(invariant_sys_regs));
2567 if (!r)
2568 return -ENOENT;
2569
2570 err = reg_from_user(&val, uaddr, id);
2571 if (err)
2572 return err;
2573
2574 /* This is what we mean by invariant: you can't change it. */
2575 if (r->val != val)
2576 return -EINVAL;
2577
2578 return 0;
2579 }
2580
is_valid_cache(u32 val)2581 static bool is_valid_cache(u32 val)
2582 {
2583 u32 level, ctype;
2584
2585 if (val >= CSSELR_MAX)
2586 return false;
2587
2588 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2589 level = (val >> 1);
2590 ctype = (cache_levels >> (level * 3)) & 7;
2591
2592 switch (ctype) {
2593 case 0: /* No cache */
2594 return false;
2595 case 1: /* Instruction cache only */
2596 return (val & 1);
2597 case 2: /* Data cache only */
2598 case 4: /* Unified cache */
2599 return !(val & 1);
2600 case 3: /* Separate instruction and data caches */
2601 return true;
2602 default: /* Reserved: we can't know instruction or data. */
2603 return false;
2604 }
2605 }
2606
demux_c15_get(u64 id, void __user *uaddr)2607 static int demux_c15_get(u64 id, void __user *uaddr)
2608 {
2609 u32 val;
2610 u32 __user *uval = uaddr;
2611
2612 /* Fail if we have unknown bits set. */
2613 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2614 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2615 return -ENOENT;
2616
2617 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2618 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2619 if (KVM_REG_SIZE(id) != 4)
2620 return -ENOENT;
2621 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2622 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2623 if (!is_valid_cache(val))
2624 return -ENOENT;
2625
2626 return put_user(get_ccsidr(val), uval);
2627 default:
2628 return -ENOENT;
2629 }
2630 }
2631
demux_c15_set(u64 id, void __user *uaddr)2632 static int demux_c15_set(u64 id, void __user *uaddr)
2633 {
2634 u32 val, newval;
2635 u32 __user *uval = uaddr;
2636
2637 /* Fail if we have unknown bits set. */
2638 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2639 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2640 return -ENOENT;
2641
2642 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2643 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2644 if (KVM_REG_SIZE(id) != 4)
2645 return -ENOENT;
2646 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2647 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2648 if (!is_valid_cache(val))
2649 return -ENOENT;
2650
2651 if (get_user(newval, uval))
2652 return -EFAULT;
2653
2654 /* This is also invariant: you can't change it. */
2655 if (newval != get_ccsidr(val))
2656 return -EINVAL;
2657 return 0;
2658 default:
2659 return -ENOENT;
2660 }
2661 }
2662
kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)2663 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2664 {
2665 const struct sys_reg_desc *r;
2666 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2667
2668 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2669 return demux_c15_get(reg->id, uaddr);
2670
2671 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2672 return -ENOENT;
2673
2674 r = index_to_sys_reg_desc(vcpu, reg->id);
2675 if (!r)
2676 return get_invariant_sys_reg(reg->id, uaddr);
2677
2678 /* Check for regs disabled by runtime config */
2679 if (sysreg_hidden(vcpu, r))
2680 return -ENOENT;
2681
2682 if (r->get_user)
2683 return (r->get_user)(vcpu, r, reg, uaddr);
2684
2685 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2686 }
2687
kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)2688 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2689 {
2690 const struct sys_reg_desc *r;
2691 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2692
2693 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2694 return demux_c15_set(reg->id, uaddr);
2695
2696 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2697 return -ENOENT;
2698
2699 r = index_to_sys_reg_desc(vcpu, reg->id);
2700 if (!r)
2701 return set_invariant_sys_reg(reg->id, uaddr);
2702
2703 /* Check for regs disabled by runtime config */
2704 if (sysreg_hidden(vcpu, r))
2705 return -ENOENT;
2706
2707 if (r->set_user)
2708 return (r->set_user)(vcpu, r, reg, uaddr);
2709
2710 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2711 }
2712
num_demux_regs(void)2713 static unsigned int num_demux_regs(void)
2714 {
2715 unsigned int i, count = 0;
2716
2717 for (i = 0; i < CSSELR_MAX; i++)
2718 if (is_valid_cache(i))
2719 count++;
2720
2721 return count;
2722 }
2723
write_demux_regids(u64 __user *uindices)2724 static int write_demux_regids(u64 __user *uindices)
2725 {
2726 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2727 unsigned int i;
2728
2729 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2730 for (i = 0; i < CSSELR_MAX; i++) {
2731 if (!is_valid_cache(i))
2732 continue;
2733 if (put_user(val | i, uindices))
2734 return -EFAULT;
2735 uindices++;
2736 }
2737 return 0;
2738 }
2739
sys_reg_to_index(const struct sys_reg_desc *reg)2740 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2741 {
2742 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2743 KVM_REG_ARM64_SYSREG |
2744 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2745 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2746 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2747 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2748 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2749 }
2750
copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)2751 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2752 {
2753 if (!*uind)
2754 return true;
2755
2756 if (put_user(sys_reg_to_index(reg), *uind))
2757 return false;
2758
2759 (*uind)++;
2760 return true;
2761 }
2762
walk_one_sys_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 __user **uind, unsigned int *total)2763 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2764 const struct sys_reg_desc *rd,
2765 u64 __user **uind,
2766 unsigned int *total)
2767 {
2768 /*
2769 * Ignore registers we trap but don't save,
2770 * and for which no custom user accessor is provided.
2771 */
2772 if (!(rd->reg || rd->get_user))
2773 return 0;
2774
2775 if (sysreg_hidden(vcpu, rd))
2776 return 0;
2777
2778 if (!copy_reg_to_user(rd, uind))
2779 return -EFAULT;
2780
2781 (*total)++;
2782 return 0;
2783 }
2784
2785 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)2786 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2787 {
2788 const struct sys_reg_desc *i2, *end2;
2789 unsigned int total = 0;
2790 int err;
2791
2792 i2 = sys_reg_descs;
2793 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2794
2795 while (i2 != end2) {
2796 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
2797 if (err)
2798 return err;
2799 }
2800 return total;
2801 }
2802
kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)2803 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2804 {
2805 return ARRAY_SIZE(invariant_sys_regs)
2806 + num_demux_regs()
2807 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2808 }
2809
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)2810 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2811 {
2812 unsigned int i;
2813 int err;
2814
2815 /* Then give them all the invariant registers' indices. */
2816 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2817 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2818 return -EFAULT;
2819 uindices++;
2820 }
2821
2822 err = walk_sys_regs(vcpu, uindices);
2823 if (err < 0)
2824 return err;
2825 uindices += err;
2826
2827 return write_demux_regids(uindices);
2828 }
2829
kvm_sys_reg_table_init(void)2830 void kvm_sys_reg_table_init(void)
2831 {
2832 unsigned int i;
2833 struct sys_reg_desc clidr;
2834
2835 /* Make sure tables are unique and in order. */
2836 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false));
2837 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true));
2838 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true));
2839 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true));
2840 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true));
2841 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false));
2842
2843 /* We abuse the reset function to overwrite the table itself. */
2844 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2845 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2846
2847 /*
2848 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2849 *
2850 * If software reads the Cache Type fields from Ctype1
2851 * upwards, once it has seen a value of 0b000, no caches
2852 * exist at further-out levels of the hierarchy. So, for
2853 * example, if Ctype3 is the first Cache Type field with a
2854 * value of 0b000, the values of Ctype4 to Ctype7 must be
2855 * ignored.
2856 */
2857 get_clidr_el1(NULL, &clidr); /* Ugly... */
2858 cache_levels = clidr.val;
2859 for (i = 0; i < 7; i++)
2860 if (((cache_levels >> (i*3)) & 7) == 0)
2861 break;
2862 /* Clear all higher bits. */
2863 cache_levels &= (1 << (i*3))-1;
2864 }
2865