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Searched refs:base (Results 5726 - 5750 of 18426) sorted by relevance

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/kernel/linux/linux-6.6/lib/zstd/compress/
H A Dzstd_opt.c388 const BYTE* const base = ms->window.base; in ZSTD_insertAndFindFirstIndexHash3() local
390 U32 const target = (U32)(ip - base); in ZSTD_insertAndFindFirstIndexHash3()
395 hashTable3[ZSTD_hash3Ptr(base+idx, hashLog3)] = idx; in ZSTD_insertAndFindFirstIndexHash3()
426 const BYTE* const base = ms->window.base; in ZSTD_insertBt1() local
430 const BYTE* const prefixStart = base + dictLimit; in ZSTD_insertBt1()
432 const U32 curr = (U32)(ip-base); in ZSTD_insertBt1()
486 match = base + matchIndex; in ZSTD_insertBt1()
492 match = base in ZSTD_insertBt1()
535 const BYTE* const base = ms->window.base; ZSTD_updateTree_internal() local
568 const BYTE* const base = ms->window.base; ZSTD_insertBtAndGetAllMatches() local
1050 const BYTE* const base = ms->window.base; ZSTD_compressBlock_opt_generic() local
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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_device_generated_commands.c47 for (unsigned i = 0; i < ARRAY_SIZE(pipeline->base.shaders); ++i) { in radv_get_sequence_size()
48 if (!pipeline->base.shaders[i]) in radv_get_sequence_size()
51 struct radv_userdata_locations *locs = &pipeline->base.shaders[i]->info.user_sgprs_locs; in radv_get_sequence_size()
63 align(pipeline->base.push_constant_size + 16 * pipeline->base.dynamic_offset_count, 16); in radv_get_sequence_size()
67 /* Index type write (normal reg write) + index buffer base write (64-bits, but special packet in radv_get_sequence_size()
86 if (pipeline->base.device->physical_device->rad_info.has_gfx9_scissor_bug) { in radv_get_sequence_size()
213 .base = offsetof(struct radv_dgc_params, field), .range = 4)
219 .base = (offsetof(struct radv_dgc_params, field) & ~3), .range = 4), \
226 .base
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/third_party/node/deps/v8/src/heap/
H A Dgc-tracer.cc10 #include "src/base/atomic-utils.h"
11 #include "src/base/strings.h"
233 base::MutexGuard guard(&background_counter_mutex_); in ResetForTesting()
386 static_cast<int64_t>(duration * base::Time::kMicrosecondsPerMillisecond); in UpdateStatistics()
660 base::OS::VPrint(format, arguments); in Output()
666 base::Vector<char> buffer(raw_buffer, kBufferSize); in Output()
669 base::VSNPrintF(buffer, format, arguments2); in Output()
681 base::OS::SNPrintF( in Print()
705 base::OS::GetCurrentProcessId(), in Print()
735 base in PrintNVP()
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/third_party/node/deps/v8/src/objects/
H A Dstring.cc7 #include "src/base/platform/yield-processor.h"
378 base::ScopedVector<base::uc16> smart_chars(this->length()); in MakeExternal()
399 base::SharedMutexGuard<base::kExclusive> shared_mutex_guard( in MakeExternal()
458 base::ScopedVector<uint16_t> smart_chars(this->length()); in MakeExternal()
462 base::ScopedVector<char> smart_chars(this->length()); in MakeExternal()
483 base::SharedMutexGuard<base::kExclusive> shared_mutex_guard( in MakeExternal()
950 base in CalculateLineEndsImpl()
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/kernel/linux/linux-5.10/lib/
H A Dtest_xarray.c208 unsigned long base = round_down(index, 1UL << order); in check_xa_mark_1() local
209 unsigned long next = base + (1UL << order); in check_xa_mark_1()
219 for (i = base; i < next; i++) { in check_xa_mark_1()
677 static noinline void check_xa_alloc_1(struct xarray *xa, unsigned int base) in check_xa_alloc_1() argument
683 /* An empty array should assign %base to the first alloc */ in check_xa_alloc_1()
684 xa_alloc_index(xa, base, GFP_KERNEL); in check_xa_alloc_1()
687 xa_erase_index(xa, base); in check_xa_alloc_1()
690 /* And it should assign %base again */ in check_xa_alloc_1()
691 xa_alloc_index(xa, base, GFP_KERNEL); in check_xa_alloc_1()
693 /* Allocating and then erasing a lot should not lose base */ in check_xa_alloc_1()
752 check_xa_alloc_2(struct xarray *xa, unsigned int base) check_xa_alloc_2() argument
803 check_xa_alloc_3(struct xarray *xa, unsigned int base) check_xa_alloc_3() argument
1438 unsigned long base = xas.xa_index; check_create_range_4() local
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/kernel/linux/linux-6.6/lib/
H A Dtest_xarray.c208 unsigned long base = round_down(index, 1UL << order); in check_xa_mark_1() local
209 unsigned long next = base + (1UL << order); in check_xa_mark_1()
219 for (i = base; i < next; i++) { in check_xa_mark_1()
677 static noinline void check_xa_alloc_1(struct xarray *xa, unsigned int base) in check_xa_alloc_1() argument
683 /* An empty array should assign %base to the first alloc */ in check_xa_alloc_1()
684 xa_alloc_index(xa, base, GFP_KERNEL); in check_xa_alloc_1()
687 xa_erase_index(xa, base); in check_xa_alloc_1()
690 /* And it should assign %base again */ in check_xa_alloc_1()
691 xa_alloc_index(xa, base, GFP_KERNEL); in check_xa_alloc_1()
693 /* Allocating and then erasing a lot should not lose base */ in check_xa_alloc_1()
752 check_xa_alloc_2(struct xarray *xa, unsigned int base) check_xa_alloc_2() argument
803 check_xa_alloc_3(struct xarray *xa, unsigned int base) check_xa_alloc_3() argument
1438 unsigned long base = xas.xa_index; check_create_range_4() local
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/third_party/mesa3d/src/panfrost/vulkan/
H A Dpanvk_vX_meta_copy.c629 panvk_per_arch(meta_emit_viewport)(&cmdbuf->desc_pool.base, in panvk_meta_copy_img2img()
640 pan_pool_upload_aligned(&cmdbuf->desc_pool.base, dst_rect, in panvk_meta_copy_img2img()
663 panvk_meta_copy_img_emit_texture(pdev, &cmdbuf->desc_pool.base, &srcview); in panvk_meta_copy_img2img()
665 panvk_meta_copy_img_emit_sampler(pdev, &cmdbuf->desc_pool.base); in panvk_meta_copy_img2img()
688 pan_pool_upload_aligned(&cmdbuf->desc_pool.base, src_rect, in panvk_meta_copy_img2img()
707 job = panvk_meta_copy_emit_tiler_job(&cmdbuf->desc_pool.base, in panvk_meta_copy_img2img()
733 panvk_meta_copy_img2img_shader(&dev->pdev, &dev->meta.bin_pool.base, in panvk_meta_copy_img2img_init()
739 panvk_meta_copy_to_img_emit_rsd(&dev->pdev, &dev->meta.desc_pool.base, in panvk_meta_copy_img2img_init()
751 panvk_meta_copy_img2img_shader(&dev->pdev, &dev->meta.bin_pool.base, in panvk_meta_copy_img2img_init()
757 panvk_meta_copy_to_img_emit_rsd(&dev->pdev, &dev->meta.desc_pool.base, in panvk_meta_copy_img2img_init()
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/foundation/arkui/ace_engine/frameworks/core/components/svg/
H A Drender_svg_base.cpp30 { ATTR_NAME_FILL, [](RenderSvgBase& base) -> Color { return base.GetFillState().GetColor(); } },
31 { ATTR_NAME_STROKE, [](RenderSvgBase& base) -> Color { return base.GetStrokeState().GetColor(); } },
35 { ATTR_NAME_STROKE_WIDTH, [](RenderSvgBase& base) -> Dimension { return base.GetStrokeState().GetLineWidth(); } },
36 { ATTR_NAME_FONT_SIZE, [](RenderSvgBase& base) -> Dimension { return base.GetTextStyle().GetFontSize(); } },
41 [](RenderSvgBase& base) -> double { return base
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/kernel/linux/linux-5.10/block/partitions/
H A Dldm.c342 * @base: Offset, into @state->bdev, of the database
354 unsigned long base, struct ldmdb *ldb) in ldm_validate_tocblocks()
381 data = read_part_sector(state, base + off[i], &sect); in ldm_validate_tocblocks()
418 * @base: Offset, into @bdev, of the database
428 unsigned long base, struct ldmdb *ldb) in ldm_validate_vmdb()
441 data = read_part_sector(state, base + OFF_VMDB, &sect); in ldm_validate_vmdb()
611 * @base: Size of the previous fixed width fields
621 static int ldm_relative(const u8 *buffer, int buflen, int base, int offset) in ldm_relative() argument
624 base += offset; in ldm_relative()
625 if (!buffer || offset < 0 || base > bufle in ldm_relative()
353 ldm_validate_tocblocks(struct parsed_partitions *state, unsigned long base, struct ldmdb *ldb) ldm_validate_tocblocks() argument
427 ldm_validate_vmdb(struct parsed_partitions *state, unsigned long base, struct ldmdb *ldb) ldm_validate_vmdb() argument
1352 ldm_get_vblks(struct parsed_partitions *state, unsigned long base, struct ldmdb *ldb) ldm_get_vblks() argument
1443 unsigned long base; ldm_partition() local
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/kernel/linux/linux-5.10/arch/powerpc/platforms/ps3/
H A Dmm.c67 * @base: base address
69 * @offset: difference between base and rm.size
74 u64 base; member
114 DBG("%s:%d: map.r1.base = %llxh\n", func, line, m->r1.base); in _debug_dump_map()
222 result = ps3_repository_read_highmem_info(0, &r->base, &r->size); in ps3_mm_get_repository_highmem()
227 if (!r->base || !r->size) { in ps3_mm_get_repository_highmem()
232 r->offset = r->base - map.rm.size; in ps3_mm_get_repository_highmem()
235 __func__, __LINE__, r->base, in ps3_mm_get_repository_highmem()
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/kernel/linux/linux-6.6/arch/powerpc/platforms/ps3/
H A Dmm.c66 * @base: base address
68 * @offset: difference between base and rm.size
73 u64 base; member
113 DBG("%s:%d: map.r1.base = %llxh\n", func, line, m->r1.base); in _debug_dump_map()
223 result = ps3_repository_read_highmem_info(0, &r->base, &r->size); in ps3_mm_get_repository_highmem()
228 if (!r->base || !r->size) { in ps3_mm_get_repository_highmem()
233 r->offset = r->base - map.rm.size; in ps3_mm_get_repository_highmem()
236 __func__, __LINE__, r->base, in ps3_mm_get_repository_highmem()
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/kernel/linux/linux-5.10/drivers/ide/
H A Dhpt366.c102 * with only the chip type and its specific base DPLL frequency, the highest
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
798 unsigned long base = hwif->extra_base; in hpt3xxn_set_clock() local
799 u8 scr2 = inb(base + 0x6b); in hpt3xxn_set_clock()
805 outb(0x80, base + 0x63); in hpt3xxn_set_clock()
806 outb(0x80, base + 0x67); in hpt3xxn_set_clock()
809 outb(mode, base + 0x6b); in hpt3xxn_set_clock()
810 outb(0xc0, base + 0x69); in hpt3xxn_set_clock()
816 outb(inb(base + 0x60) | 0x32, base in hpt3xxn_set_clock()
1225 unsigned long flags, base = ide_pci_dma_base(hwif, d); init_dma_hpt366() local
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/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
H A Dcoresight-tmc-etr.c75 * b11 - Link. The address points to the base of next table.
104 * @hwaddr: hwaddress used by the TMC, which is the base
420 unsigned long base; in tmc_sg_daddr_to_vaddr() local
425 base = (unsigned long)sg_table->table_vaddr; in tmc_sg_daddr_to_vaddr()
428 base = (unsigned long)sg_table->data_vaddr; in tmc_sg_daddr_to_vaddr()
434 return base + offset; in tmc_sg_daddr_to_vaddr()
585 /* TMC should use table base address for DBA */ in tmc_init_etr_sg_table()
950 status = readl_relaxed(drvdata->base + TMC_STS); in tmc_sync_etr_buf()
976 CS_UNLOCK(drvdata->base); in __tmc_etr_enable_hw()
981 writel_relaxed(etr_buf->size / 4, drvdata->base in __tmc_etr_enable_hw()
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/kernel/linux/linux-5.10/drivers/pci/controller/
H A Dpcie-iproc.c433 return readl(pcie->base + offset); in iproc_pcie_read_reg()
444 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
491 return (pcie->base + offset); in iproc_pcie_map_ep_cfg_reg()
658 return (pcie->base + offset); in iproc_pcie_map_cfg_bus()
896 OARR_VALID, pcie->base + oarr_offset); in iproc_pcie_ob_write()
897 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); in iproc_pcie_ob_write()
900 writel(lower_32_bits(pci_addr), pcie->base + omap_offset); in iproc_pcie_ob_write()
901 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); in iproc_pcie_ob_write()
906 readl(pcie->base + oarr_offset), in iproc_pcie_ob_write()
907 readl(pcie->base in iproc_pcie_ob_write()
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/kernel/linux/linux-5.10/drivers/gpu/drm/stm/
H A Dltdc.c241 static inline u32 reg_read(void __iomem *base, u32 reg) in reg_read() argument
243 return readl_relaxed(base + reg); in reg_read()
246 static inline void reg_write(void __iomem *base, u32 reg, u32 val) in reg_write() argument
248 writel_relaxed(val, base + reg); in reg_write()
251 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) in reg_set() argument
253 reg_write(base, reg, reg_read(base, reg) | mask); in reg_set()
256 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) in reg_clear() argument
258 reg_write(base, reg, reg_read(base, re in reg_clear()
261 reg_update_bits(void __iomem *base, u32 reg, u32 mask, u32 val) reg_update_bits() argument
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/kernel/linux/linux-6.6/drivers/memory/
H A Dmtk-smi.c146 void __iomem *base; /* only for gen2 */ member
154 void __iomem *base; member
227 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); in mtk_smi_larb_config_port_mt8167()
235 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); in mtk_smi_larb_config_port_mt8173()
251 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); in mtk_smi_larb_config_port_gen2_general()
254 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); in mtk_smi_larb_config_port_gen2_general()
258 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); in mtk_smi_larb_config_port_gen2_general()
261 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); in mtk_smi_larb_config_port_gen2_general()
278 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); in mtk_smi_larb_config_port_gen2_general()
281 writel(reg, larb->base in mtk_smi_larb_config_port_gen2_general()
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/kernel/linux/linux-6.6/drivers/pci/controller/
H A Dpcie-iproc.c423 return readl(pcie->base + offset); in iproc_pcie_read_reg()
434 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
477 return (pcie->base + offset); in iproc_pcie_map_ep_cfg_reg()
640 return (pcie->base + offset); in iproc_pcie_map_cfg_bus()
875 OARR_VALID, pcie->base + oarr_offset); in iproc_pcie_ob_write()
876 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); in iproc_pcie_ob_write()
879 writel(lower_32_bits(pci_addr), pcie->base + omap_offset); in iproc_pcie_ob_write()
880 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); in iproc_pcie_ob_write()
885 readl(pcie->base + oarr_offset), in iproc_pcie_ob_write()
886 readl(pcie->base in iproc_pcie_ob_write()
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/kernel/linux/linux-6.6/block/partitions/
H A Dldm.c342 * @base: Offset, into @state->disk, of the database
354 unsigned long base, struct ldmdb *ldb) in ldm_validate_tocblocks()
381 data = read_part_sector(state, base + off[i], &sect); in ldm_validate_tocblocks()
418 * @base: Offset, into @bdev, of the database
428 unsigned long base, struct ldmdb *ldb) in ldm_validate_vmdb()
441 data = read_part_sector(state, base + OFF_VMDB, &sect); in ldm_validate_vmdb()
611 * @base: Size of the previous fixed width fields
621 static int ldm_relative(const u8 *buffer, int buflen, int base, int offset) in ldm_relative() argument
624 base += offset; in ldm_relative()
625 if (!buffer || offset < 0 || base > bufle in ldm_relative()
353 ldm_validate_tocblocks(struct parsed_partitions *state, unsigned long base, struct ldmdb *ldb) ldm_validate_tocblocks() argument
427 ldm_validate_vmdb(struct parsed_partitions *state, unsigned long base, struct ldmdb *ldb) ldm_validate_vmdb() argument
1343 ldm_get_vblks(struct parsed_partitions *state, unsigned long base, struct ldmdb *ldb) ldm_get_vblks() argument
1434 unsigned long base; ldm_partition() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_plane.c19 struct drm_plane base; member
24 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
88 drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode); in mdp5_plane_atomic_print_state()
89 drm_printf(p, "\tzpos=%u\n", pstate->base.zpos); in mdp5_plane_atomic_print_state()
90 drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos); in mdp5_plane_atomic_print_state()
91 drm_printf(p, "\talpha=%u\n", pstate->base.alpha); in mdp5_plane_atomic_print_state()
107 __drm_atomic_helper_plane_reset(plane, &mdp5_state->base); in mdp5_plane_reset()
123 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base); in mdp5_plane_duplicate_state()
125 return &mdp5_state->base; in mdp5_plane_duplicate_state()
167 struct msm_kms *kms = &mdp5_kms->base in mdp5_plane_cleanup_fb()
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/kernel/linux/linux-6.6/sound/soc/apple/
H A Dmca.c46 /* Relative to cluster base */
85 /* Relative to serdes unit base */
110 /* Relative to switch base */
130 __iomem void *base; member
169 __iomem void *ptr = cl->base + regoffset; in mca_modify()
217 WARN_ON(readl_relaxed(cl->base + serdes_unit + REG_SERDES_STATUS) & in mca_fe_early_trigger()
287 writel_relaxed(cl->no + 1, cl->base + REG_SYNCGEN_MCLK_SEL); in mca_fe_enable_clocks()
397 __iomem void *serdes_base = cl->base + serdes_unit; in mca_configure_serdes()
527 cl->base + CLUSTER_TX_OFF + REG_TX_SERDES_BITSTART); in mca_fe_set_fmt()
529 cl->base in mca_fe_set_fmt()
1015 void __iomem *base; apple_mca_probe() local
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state_shaders.cpp57 !info->base.workgroup_size_variable && in si_determine_wave_size()
58 info->base.workgroup_size[0] * in si_determine_wave_size()
59 info->base.workgroup_size[1] * in si_determine_wave_size()
60 info->base.workgroup_size[2] <= 32) in si_determine_wave_size()
98 if (stage == MESA_SHADER_FRAGMENT && info->base.fs.uses_discard && in si_determine_wave_size()
179 sel->info.base.fs.needs_quad_helper_invocations && in si_get_ir_cache_key()
180 sel->info.base.fs.uses_discard && in si_get_ir_cache_key()
517 enum tess_primitive_mode tes_prim_mode = info->base.tess._primitive_mode; in si_set_tesseval_regs()
518 unsigned tes_spacing = info->base.tess.spacing; in si_set_tesseval_regs()
519 bool tes_vertex_order_cw = !info->base in si_set_tesseval_regs()
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/kernel/linux/linux-5.10/arch/x86/lib/
H A Dinsn-eval.c262 * The operand register, @regoff, is represented as the offset from the base of
492 * If ModRM.mod is 0 and SIB.base == 5, the base of the in get_reg_offset()
633 * from the base of the GDT. As bits [15:3] of the segment selector in get_desc()
647 * insn_get_seg_base() - Obtain base address of segment descriptor.
651 * Obtain the base address of the segment as indicated by the segment descriptor
657 * In protected mode, base address of the segment. Zero in long mode,
681 * Only FS or GS will have a base address, the rest of in insn_get_seg_base()
684 unsigned long base; in insn_get_seg_base() local
687 rdmsrl(MSR_FS_BASE, base); in insn_get_seg_base()
878 get_seg_base_limit(struct insn *insn, struct pt_regs *regs, int regoff, unsigned long *base, unsigned long *limit) get_seg_base_limit() argument
1115 long base, indx; get_eff_addr_sib() local
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/kernel/linux/linux-5.10/arch/x86/kernel/cpu/
H A Dcacheinfo.c878 struct _cpuid4_info_regs *base) in __cache_amd_cpumap_setup()
904 nshared = base->eax.split.num_threads_sharing + 1; in __cache_amd_cpumap_setup()
935 struct _cpuid4_info_regs *base) in __cache_cpumap_setup()
945 if (__cache_amd_cpumap_setup(cpu, index, base)) in __cache_cpumap_setup()
950 num_threads_sharing = 1 + base->eax.split.num_threads_sharing; in __cache_cpumap_setup()
971 struct _cpuid4_info_regs *base) in ci_leaf_init()
973 this_leaf->id = base->id; in ci_leaf_init()
975 this_leaf->level = base->eax.split.level; in ci_leaf_init()
976 this_leaf->type = cache_type_map[base->eax.split.type]; in ci_leaf_init()
978 base in ci_leaf_init()
877 __cache_amd_cpumap_setup(unsigned int cpu, int index, struct _cpuid4_info_regs *base) __cache_amd_cpumap_setup() argument
934 __cache_cpumap_setup(unsigned int cpu, int index, struct _cpuid4_info_regs *base) __cache_cpumap_setup() argument
970 ci_leaf_init(struct cacheinfo *this_leaf, struct _cpuid4_info_regs *base) ci_leaf_init() argument
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/kernel/linux/linux-5.10/crypto/
H A Dchacha20poly1305.c597 if (chacha->base.cra_blocksize != 1) in chachapoly_create()
601 if (snprintf(inst->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, in chachapoly_create()
602 "%s(%s,%s)", name, chacha->base.cra_name, in chachapoly_create()
603 poly->base.cra_name) >= CRYPTO_MAX_ALG_NAME) in chachapoly_create()
605 if (snprintf(inst->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, in chachapoly_create()
606 "%s(%s,%s)", name, chacha->base.cra_driver_name, in chachapoly_create()
607 poly->base.cra_driver_name) >= CRYPTO_MAX_ALG_NAME) in chachapoly_create()
610 inst->alg.base.cra_priority = (chacha->base.cra_priority + in chachapoly_create()
611 poly->base in chachapoly_create()
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/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/
H A Domap_crtc.c18 #define to_omap_crtc_state(x) container_of(x, struct omap_crtc_state, base)
22 struct drm_crtc_state base; member
29 #define to_omap_crtc(x) container_of(x, struct omap_crtc, base)
32 struct drm_crtc base; member
191 omap_crtc_set_enabled(&omap_crtc->base, true); in omap_crtc_dss_enable()
202 omap_crtc_set_enabled(&omap_crtc->base, false); in omap_crtc_dss_disable()
234 struct drm_device *dev = omap_crtc->base.dev; in omap_crtc_dss_register_framedone()
253 struct drm_device *dev = omap_crtc->base.dev; in omap_crtc_dss_unregister_framedone()
294 struct drm_device *dev = omap_crtc->base.dev; in omap_crtc_vblank_irq()
367 struct drm_device *dev = omap_crtc->base in omap_crtc_manual_display_update()
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