Lines Matching refs:base
146 void __iomem *base; /* only for gen2 */
154 void __iomem *base;
227 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
235 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
251 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
254 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
258 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
261 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
278 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
281 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
459 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
460 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON,
471 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
541 larb->base = devm_platform_ioremap_resource(pdev, 0);
542 if (IS_ERR(larb->base))
543 return PTR_ERR(larb->base);
763 * for mtk smi gen 1, we need to get the ao(always on) base to config
766 * base.
781 common->base = devm_platform_ioremap_resource(pdev, 0);
782 if (IS_ERR(common->base))
783 return PTR_ERR(common->base);
823 writel_relaxed(init[i].value, common->base + init[i].offset);
825 writel(bus_sel, common->base + SMI_BUS_SEL);