Lines Matching refs:base
102 * with only the chip type and its specific base DPLL frequency, the highest
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
798 unsigned long base = hwif->extra_base;
799 u8 scr2 = inb(base + 0x6b);
805 outb(0x80, base + 0x63);
806 outb(0x80, base + 0x67);
809 outb(mode, base + 0x6b);
810 outb(0xc0, base + 0x69);
816 outb(inb(base + 0x60) | 0x32, base + 0x60);
817 outb(inb(base + 0x64) | 0x32, base + 0x64);
820 outb(0x00, base + 0x69);
823 outb(0x00, base + 0x63);
824 outb(0x00, base + 0x67);
1008 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1225 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1228 if (base == 0)
1231 hwif->dma_base = base;
1239 dma_old = inb(base + 2);
1250 outb(dma_new, base + 2);
1255 hwif->name, base, base + 7);
1257 hwif->extra_base = base + (hwif->channel ? 8 : 16);