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/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_bld_blend_aos.c68 struct lp_build_context base; member
104 return bld->base.zero; in lp_build_blend_factor_unswizzled()
106 return bld->base.one; in lp_build_blend_factor_unswizzled()
116 return bld->base.one; in lp_build_blend_factor_unswizzled()
124 bld->saturate = lp_build_min(&bld->base, src_alpha, bld->base.zero); in lp_build_blend_factor_unswizzled()
126 else if (bld->base.type.norm && bld->base.type.sign) { in lp_build_blend_factor_unswizzled()
134 inv_dst = lp_build_max(&bld->base, bld->base in lp_build_blend_factor_unswizzled()
[all...]
/third_party/node/deps/v8/src/compiler/
H A Daccess-info.h72 base::Optional<JSObjectRef> holder);
77 Type field_type, MapRef field_owner_map, base::Optional<MapRef> field_map,
78 base::Optional<JSObjectRef> holder,
79 base::Optional<MapRef> transition_map);
84 Type field_type, MapRef field_owner_map, base::Optional<MapRef> field_map,
85 base::Optional<JSObjectRef> holder,
86 base::Optional<MapRef> transition_map);
88 Zone* zone, MapRef receiver_map, base::Optional<ObjectRef> constant,
89 base::Optional<JSObjectRef> holder);
98 Zone* zone, MapRef receiver_map, base
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/third_party/node/deps/v8/src/strings/
H A Duri.cc18 bool IsReservedPredicate(base::uc16 c) { in IsReservedPredicate()
48 std::vector<base::uc16>* buffer) { in DecodeOctets()
50 base::uc32 value = unibrow::Utf8::ValueOf(octets, length, &cursor); in DecodeOctets()
57 static_cast<base::uc32>(unibrow::Utf16::kMaxNonSurrogateCharCode)) { in DecodeOctets()
66 int TwoDigitHex(base::uc16 character1, base::uc16 character2) { in TwoDigitHex()
68 int high = base::HexValue(character1); in TwoDigitHex()
71 int low = base::HexValue(character2); in TwoDigitHex()
77 void AddToBuffer(base::uc16 decoded, String::FlatContent* uri_content, in AddToBuffer()
81 base in AddToBuffer()
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/third_party/mesa3d/src/gallium/targets/d3dadapter9/
H A Ddrm.c102 struct d3dadapter9_context base; member
229 ctx->base.destroy = drm_destroy; in drm_create_adapter()
235 ctx->base.linear_framebuffer = different_device; in drm_create_adapter()
244 ctx->base.hal = pipe_loader_create_screen(ctx->dev); in drm_create_adapter()
245 if (!ctx->base.hal) { in drm_create_adapter()
247 drm_destroy(&ctx->base); in drm_create_adapter()
251 if (!ctx->base.hal->get_param(ctx->base.hal, PIPE_CAP_DMABUF)) { in drm_create_adapter()
254 drm_destroy(&ctx->base); in drm_create_adapter()
261 ctx->base in drm_create_adapter()
[all...]
/third_party/typescript/tests/baselines/reference/
H A DarrayBestCommonTypes.js4 class base implements iface { }
6 class derived extends base { }
33 var t1: { x: number; y: base; }[] = [{ x: 7, y: new derived() }, { x: 5, y: new base() }];
34 var t2: { x: boolean; y: base; }[] = [{ x: true, y: new derived() }, { x: false, y: new base() }];
35 var t3: { x: string; y: base; }[] = [{ x: undefined, y: new base() }, { x: '', y: new derived() }];
44 var baseObj = new base();
57 class base implement
[all...]
/kernel/linux/linux-5.10/arch/arm/common/
H A Dlocomo.c66 void __iomem *base; member
81 * locomo_dev will be set to the chip base plus offset. If offset is
147 req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; in locomo_handler()
171 r = locomo_readl(lchip->base + LOCOMO_ICR); in locomo_mask_irq()
173 locomo_writel(r, lchip->base + LOCOMO_ICR); in locomo_mask_irq()
180 r = locomo_readl(lchip->base + LOCOMO_ICR); in locomo_unmask_irq()
182 locomo_writel(r, lchip->base + LOCOMO_ICR); in locomo_unmask_irq()
247 dev->mapbase = lchip->base + info->offset; in locomo_init_one_child()
287 save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */ in locomo_suspend()
288 locomo_writel(0x00, lchip->base in locomo_suspend()
[all...]
/kernel/linux/linux-6.6/arch/arm/common/
H A Dlocomo.c65 void __iomem *base; member
80 * locomo_dev will be set to the chip base plus offset. If offset is
146 req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; in locomo_handler()
170 r = locomo_readl(lchip->base + LOCOMO_ICR); in locomo_mask_irq()
172 locomo_writel(r, lchip->base + LOCOMO_ICR); in locomo_mask_irq()
179 r = locomo_readl(lchip->base + LOCOMO_ICR); in locomo_unmask_irq()
181 locomo_writel(r, lchip->base + LOCOMO_ICR); in locomo_unmask_irq()
246 dev->mapbase = lchip->base + info->offset; in locomo_init_one_child()
286 save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */ in locomo_suspend()
287 locomo_writel(0x00, lchip->base in locomo_suspend()
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/kernel/linux/linux-5.10/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c78 void __iomem *base; member
311 static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val) in dsi_phy_tst_set() argument
318 writel(reg_write, base + PHY_TST_CTRL1); in dsi_phy_tst_set()
319 writel(0x02, base + PHY_TST_CTRL0); in dsi_phy_tst_set()
320 writel(0x00, base + PHY_TST_CTRL0); in dsi_phy_tst_set()
325 writel(val, base + PHY_TST_CTRL1); in dsi_phy_tst_set()
326 writel(0x02, base + PHY_TST_CTRL0); in dsi_phy_tst_set()
327 writel(0x00, base + PHY_TST_CTRL0); in dsi_phy_tst_set()
330 static void dsi_set_phy_timer(void __iomem *base, in dsi_set_phy_timer() argument
340 writel(val, base in dsi_set_phy_timer()
363 dsi_set_mipi_phy(void __iomem *base, struct mipi_phy_params *phy, u32 lanes) dsi_set_mipi_phy() argument
447 dsi_set_mode_timing(void __iomem *base, u32 lane_byte_clk_kHz, struct drm_display_mode *mode, enum mipi_dsi_pixel_format format) dsi_set_mode_timing() argument
513 dsi_set_video_mode(void __iomem *base, unsigned long flags) dsi_set_video_mode() argument
543 void __iomem *base = ctx->base; dsi_mipi_init() local
575 void __iomem *base = ctx->base; dsi_encoder_disable() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/hisilicon/kirin/
H A Ddw_drm_dsi.c79 void __iomem *base; member
312 static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val) in dsi_phy_tst_set() argument
319 writel(reg_write, base + PHY_TST_CTRL1); in dsi_phy_tst_set()
320 writel(0x02, base + PHY_TST_CTRL0); in dsi_phy_tst_set()
321 writel(0x00, base + PHY_TST_CTRL0); in dsi_phy_tst_set()
326 writel(val, base + PHY_TST_CTRL1); in dsi_phy_tst_set()
327 writel(0x02, base + PHY_TST_CTRL0); in dsi_phy_tst_set()
328 writel(0x00, base + PHY_TST_CTRL0); in dsi_phy_tst_set()
331 static void dsi_set_phy_timer(void __iomem *base, in dsi_set_phy_timer() argument
341 writel(val, base in dsi_set_phy_timer()
364 dsi_set_mipi_phy(void __iomem *base, struct mipi_phy_params *phy, u32 lanes) dsi_set_mipi_phy() argument
448 dsi_set_mode_timing(void __iomem *base, u32 lane_byte_clk_kHz, struct drm_display_mode *mode, enum mipi_dsi_pixel_format format) dsi_set_mode_timing() argument
514 dsi_set_video_mode(void __iomem *base, unsigned long flags) dsi_set_video_mode() argument
544 void __iomem *base = ctx->base; dsi_mipi_init() local
576 void __iomem *base = ctx->base; dsi_encoder_disable() local
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/kernel/linux/linux-5.10/drivers/tty/
H A Disicom.c89 * 06/01/05 Alan Cox Merged the ISI and base kernel strands
137 #define InterruptTheCard(base) outw(0, (base) + 0xc)
138 #define ClearInterrupt(base) inw((base) + 0x0a)
185 unsigned long base; member
219 static int WaitTillCardIsFree(unsigned long base) in WaitTillCardIsFree() argument
223 while (!(inw(base + 0xe) & 0x1) && count++ < 100) in WaitTillCardIsFree()
226 return !(inw(base + 0xe) & 0x1); in WaitTillCardIsFree()
231 unsigned long base in lock_card() local
262 unsigned long base = card->base; raise_dtr() local
278 unsigned long base = card->base; drop_dtr() local
294 unsigned long base = card->base; raise_rts() local
310 unsigned long base = card->base; drop_rts() local
328 unsigned long base = card->base; isicom_dtr_rts() local
352 unsigned long base = card->base; drop_dtr_rts() local
395 unsigned long flags, base; isicom_tx() local
512 unsigned long base; isicom_interrupt() local
679 unsigned long base = card->base; isicom_config_port() local
1034 unsigned long base = card->base; isicom_send_break() local
1277 unsigned long base = board->base; reset_card() local
1339 unsigned long base = board->base; load_firmware() local
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/kernel/linux/linux-5.10/drivers/i2c/busses/
H A Di2c-wmt.c86 void __iomem *base; member
98 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { in wmt_i2c_wait_bus_not_busy()
143 writew(0, i2c_dev->base + REG_CDR); in wmt_i2c_write()
145 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); in wmt_i2c_write()
149 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
151 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write()
153 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
155 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write()
167 writew(tcr_val, i2c_dev->base + REG_TCR); in wmt_i2c_write()
170 val = readw(i2c_dev->base in wmt_i2c_write()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_9_0_sm8550.h24 .base = 0, .len = 0x494,
45 .base = 0x15000, .len = 0x290,
50 .base = 0x16000, .len = 0x290,
55 .base = 0x17000, .len = 0x290,
60 .base = 0x18000, .len = 0x290,
65 .base = 0x19000, .len = 0x290,
70 .base = 0x1a000, .len = 0x290,
79 .base = 0x4000, .len = 0x344,
87 .base = 0x6000, .len = 0x344,
95 .base
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/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-wmt.c86 void __iomem *base; member
98 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { in wmt_i2c_wait_bus_not_busy()
143 writew(0, i2c_dev->base + REG_CDR); in wmt_i2c_write()
145 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); in wmt_i2c_write()
149 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
151 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write()
153 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write()
155 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write()
167 writew(tcr_val, i2c_dev->base + REG_TCR); in wmt_i2c_write()
170 val = readw(i2c_dev->base in wmt_i2c_write()
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/third_party/skia/third_party/externals/zlib/google/
H A Dzip_reader.cc9 #include "base/bind.h"
10 #include "base/files/file.h"
11 #include "base/logging.h"
12 #include "base/macros.h"
13 #include "base/strings/string_util.h"
14 #include "base/strings/utf_string_conversions.h"
15 #include "base/threading/sequenced_task_runner_handle.h"
50 void SetTimeModified(const base::Time& time) override;
79 void StringWriterDelegate::SetTimeModified(const base::Time& time) { in SetTimeModified()
90 : file_path_(base in EntryInfo()
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/kernel/linux/linux-5.10/arch/mips/alchemy/common/
H A Dvss.c25 void __iomem *base = (void __iomem *)VSS_ADDR(block); in __enable_block() local
27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base in __enable_block()
56 void __iomem *base = (void __iomem *)VSS_ADDR(block); __disable_block() local
[all...]
/kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/
H A Dhaldefs.h46 nlm_read_reg(uint64_t base, uint32_t reg) in nlm_read_reg() argument
48 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; in nlm_read_reg()
54 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) in nlm_write_reg() argument
56 volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; in nlm_write_reg()
71 nlm_read_reg64(uint64_t base, uint32_t reg) in nlm_read_reg64() argument
73 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); in nlm_read_reg64()
98 nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) in nlm_write_reg64() argument
100 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); in nlm_write_reg64()
129 nlm_read_reg_xkphys(uint64_t base, uint32_t reg) in nlm_read_reg_xkphys() argument
131 return nlm_read_reg(base, re in nlm_read_reg_xkphys()
135 nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) nlm_write_reg_xkphys() argument
141 nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) nlm_read_reg64_xkphys() argument
147 nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) nlm_write_reg64_xkphys() argument
[all...]
/kernel/linux/linux-6.6/arch/mips/alchemy/common/
H A Dvss.c25 void __iomem *base = (void __iomem *)VSS_ADDR(block); in __enable_block() local
27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base in __enable_block()
56 void __iomem *base = (void __iomem *)VSS_ADDR(block); __disable_block() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dbusnv4e.c24 #define nv4e_i2c_bus(p) container_of((p), struct nv4e_i2c_bus, base)
28 struct nvkm_i2c_bus base; member
33 nv4e_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) in nv4e_i2c_bus_drive_scl() argument
35 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); in nv4e_i2c_bus_drive_scl()
36 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; in nv4e_i2c_bus_drive_scl()
41 nv4e_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) in nv4e_i2c_bus_drive_sda() argument
43 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); in nv4e_i2c_bus_drive_sda()
44 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; in nv4e_i2c_bus_drive_sda()
49 nv4e_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) in nv4e_i2c_bus_sense_scl() argument
51 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); in nv4e_i2c_bus_sense_scl()
57 nv4e_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) nv4e_i2c_bus_sense_sda() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dbusnv4e.c24 #define nv4e_i2c_bus(p) container_of((p), struct nv4e_i2c_bus, base)
28 struct nvkm_i2c_bus base; member
33 nv4e_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) in nv4e_i2c_bus_drive_scl() argument
35 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); in nv4e_i2c_bus_drive_scl()
36 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; in nv4e_i2c_bus_drive_scl()
41 nv4e_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) in nv4e_i2c_bus_drive_sda() argument
43 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); in nv4e_i2c_bus_drive_sda()
44 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; in nv4e_i2c_bus_drive_sda()
49 nv4e_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) in nv4e_i2c_bus_sense_scl() argument
51 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); in nv4e_i2c_bus_sense_scl()
57 nv4e_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) nv4e_i2c_bus_sense_sda() argument
[all...]
/kernel/linux/linux-5.10/drivers/irqchip/
H A Dirq-ath79-misc.c36 void __iomem *base = domain->host_data; in ath79_misc_irq_handler() local
41 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & in ath79_misc_irq_handler()
42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler()
62 void __iomem *base = irq_data_get_irq_chip_data(d); in ar71xx_misc_irq_unmask() local
66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
67 __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
75 void __iomem *base = irq_data_get_irq_chip_data(d); in ar71xx_misc_irq_mask() local
79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
80 __raw_writel(t & ~BIT(irq), base in ar71xx_misc_irq_mask()
88 void __iomem *base = irq_data_get_irq_chip_data(d); ar724x_misc_irq_ack() local
120 void __iomem *base = domain->host_data; ath79_misc_intc_domain_init() local
135 void __iomem *base; ath79_misc_intc_of_init() local
[all...]
/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dmmci_qcom_dml.c51 void __iomem *base = host->base + DML_OFFSET; in qcom_dma_start() local
61 config = readl_relaxed(base + DML_CONFIG); in qcom_dma_start()
64 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in qcom_dma_start()
71 base + DML_PRODUCER_BAM_TRANS_SIZE); in qcom_dma_start()
73 config = readl_relaxed(base + DML_CONFIG); in qcom_dma_start()
75 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
77 writel_relaxed(1, base + DML_PRODUCER_START); in qcom_dma_start()
81 config = readl_relaxed(base in qcom_dma_start()
122 void __iomem *base; qcom_dma_setup() local
[all...]
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dmmci_qcom_dml.c51 void __iomem *base = host->base + DML_OFFSET; in qcom_dma_start() local
61 config = readl_relaxed(base + DML_CONFIG); in qcom_dma_start()
64 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in qcom_dma_start()
71 base + DML_PRODUCER_BAM_TRANS_SIZE); in qcom_dma_start()
73 config = readl_relaxed(base + DML_CONFIG); in qcom_dma_start()
75 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
77 writel_relaxed(1, base + DML_PRODUCER_START); in qcom_dma_start()
81 config = readl_relaxed(base in qcom_dma_start()
122 void __iomem *base; qcom_dma_setup() local
[all...]
/kernel/linux/linux-6.6/drivers/irqchip/
H A Dirq-ath79-misc.c36 void __iomem *base = domain->host_data; in ath79_misc_irq_handler() local
41 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & in ath79_misc_irq_handler()
42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler()
62 void __iomem *base = irq_data_get_irq_chip_data(d); in ar71xx_misc_irq_unmask() local
66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
67 __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
75 void __iomem *base = irq_data_get_irq_chip_data(d); in ar71xx_misc_irq_mask() local
79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
80 __raw_writel(t & ~BIT(irq), base in ar71xx_misc_irq_mask()
88 void __iomem *base = irq_data_get_irq_chip_data(d); ar724x_misc_irq_ack() local
120 void __iomem *base = domain->host_data; ath79_misc_intc_domain_init() local
135 void __iomem *base; ath79_misc_intc_of_init() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_resource.c93 container_of(pool, struct dcn301_resource_pool, base)
721 return &dpp->base; in dcn301_dpp_create()
740 return &opp->base; in dcn301_opp_create()
758 return &aux_engine->base; in dcn301_aux_engine_create()
808 return &mpc30->base; in dcn301_mpc_create()
839 return &hubbub3->base; in dcn301_hubbub_create()
851 tgn10->base.inst = instance; in dcn301_timing_generator_create()
852 tgn10->base.ctx = ctx; in dcn301_timing_generator_create()
860 return &tgn10->base; in dcn301_timing_generator_create()
894 return &enc20->enc10.base; in dcn301_link_encoder_create()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dradeon_connectors.c298 radeon_connector->edid = drm_get_edid(&radeon_connector->base, in radeon_connector_get_edid()
301 radeon_connector->edid = drm_get_edid(&radeon_connector->base, in radeon_connector_get_edid()
306 radeon_connector->edid = drm_get_edid_switcheroo(&radeon_connector->base, in radeon_connector_get_edid()
309 radeon_connector->edid = drm_get_edid(&radeon_connector->base, in radeon_connector_get_edid()
553 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property()
568 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property()
583 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property()
597 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property()
611 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property()
625 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property()
[all...]

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