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/third_party/node/deps/v8/src/parsing/
H A Dliteral-buffer.cc7 #include "src/base/strings.h"
35 base::Vector<byte> new_store = in ExpandBuffer()
36 base::Vector<byte>::New(NewCapacity(min_capacity)); in ExpandBuffer()
46 base::Vector<byte> new_store; in ConvertToTwoByte()
47 int new_content_size = position_ * base::kUC16Size; in ConvertToTwoByte()
51 new_store = base::Vector<byte>::New(NewCapacity(new_content_size)); in ConvertToTwoByte()
68 void LiteralBuffer::AddTwoByteChar(base::uc32 code_unit) { in AddTwoByteChar()
72 static_cast<base::uc32>(unibrow::Utf16::kMaxNonSurrogateCharCode)) { in AddTwoByteChar()
74 position_ += base::kUC16Size; in AddTwoByteChar()
78 position_ += base in AddTwoByteChar()
[all...]
/third_party/node/deps/v8/src/snapshot/
H A Dsnapshot-source-sink.h10 #include "src/base/atomicops.h"
11 #include "src/base/logging.h"
12 #include "src/base/platform/wrappers.h"
33 explicit SnapshotByteSource(base::Vector<const byte> payload) in SnapshotByteSource()
60 base::AtomicWord* start = reinterpret_cast<base::AtomicWord*>(dest);
61 base::AtomicWord* end = start + number_of_slots;
62 for (base::AtomicWord* p = start; p < end;
63 ++p, position_ += sizeof(base::AtomicWord)) {
64 base
[all...]
/third_party/typescript/tests/baselines/reference/
H A DdecoratorOnClassConstructor2.js4 export class base { }
8 import {base} from "./0.ts"
10 export class C extends base{
19 exports.foo = exports.base = void 0;
20 var base = /** @class */ (function () {
21 function base() {
23 return base;
25 exports.base = base;
67 }(_0_ts_1.base));
[all...]
H A DdecoratorOnClassConstructor3.js4 export class base { }
8 import {base} from "./0"
12 export class C extends base{
21 exports.foo = exports.base = void 0;
22 var base = /** @class */ (function () {
23 function base() {
25 return base;
27 exports.base = base;
70 }(_0_1.base));
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c45 mem_input110->base.ctx, in set_flip_control()
53 mem_input110->base.ctx, in set_flip_control()
74 mem_input110->base.ctx, in program_pri_addr_c()
88 mem_input110->base.ctx, in program_pri_addr_c()
110 mem_input110->base.ctx, in program_pri_addr_l()
124 mem_input110->base.ctx, in program_pri_addr_l()
157 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE); in enable()
159 dm_write_reg(mem_input110->base.ctx, in enable()
202 mem_input110->base.ctx, in program_tiling()
224 mem_input110->base in program_tiling()
[all...]
/kernel/linux/linux-6.6/arch/s390/include/asm/
H A Dvx-insn-asm.h272 .macro VLVGB v, gr, index, base
273 VLVG \v, \gr, \index, \base, 0 variable
295 .macro VL v, disp, index="%r0", base
298 GR_NUM b2, \base
305 .macro VLEx vr1, disp, index="%r0", base, m3, opc variable
308 GR_NUM b2, \base
313 .macro VLEB vr1, disp, index="%r0", base, m3 variable
314 VLEx \vr1, \disp, \index, \base, \m3, 0x00 variable
316 .macro VLEH vr1, disp, index="%r0", base, m3 variable
317 VLEx \vr1, \disp, \index, \base, \m variable
319 .macro VLEF vr1, disp, index="%r0", base, m3 global() variable
320 VLEx \\vr1, \\disp, \\index, \\base, \\m3, 0x03 global() variable
322 .macro VLEG vr1, disp, index="%r0", base, m3 global() variable
323 VLEx \\vr1, \\disp, \\index, \\base, \\m3, 0x02 global() variable
347 .macro VLGV gr, vr, disp, base="%r0", m global() variable
355 .macro VLGVB gr, vr, disp, base="%r0" global() variable
356 VLGV \\gr, \\vr, \\disp, \\base, 0 global() variable
358 .macro VLGVH gr, vr, disp, base="%r0" global() variable
359 VLGV \\gr, \\vr, \\disp, \\base, 1 global() variable
361 .macro VLGVF gr, vr, disp, base="%r0" global() variable
362 VLGV \\gr, \\vr, \\disp, \\base, 2 global() variable
364 .macro VLGVG gr, vr, disp, base="%r0" global() variable
365 VLGV \\gr, \\vr, \\disp, \\base, 3 global() variable
369 .macro VLM vfrom, vto, disp, base, hint=3 global() variable
389 .macro VSTM vfrom, vto, disp, base, hint=3 global() variable
649 .macro VERLL vr1, vr3, disp, base="%r0", m4 global() variable
657 .macro VERLLB vr1, vr3, disp, base="%r0" global() variable
658 VERLL \\vr1, \\vr3, \\disp, \\base, 0 global() variable
660 .macro VERLLH vr1, vr3, disp, base="%r0" global() variable
661 VERLL \\vr1, \\vr3, \\disp, \\base, 1 global() variable
663 .macro VERLLF vr1, vr3, disp, base="%r0" global() variable
664 VERLL \\vr1, \\vr3, \\disp, \\base, 2 global() variable
666 .macro VERLLG vr1, vr3, disp, base="%r0" global() variable
667 VERLL \\vr1, \\vr3, \\disp, \\base, 3 global() variable
[all...]
/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-meson-spicc.c156 void __iomem *base; member
181 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | in meson_spicc_oen_enable()
184 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); in meson_spicc_oen_enable()
190 readl_relaxed(spicc->base + SPICC_STATREG)); in meson_spicc_txfull()
196 readl_relaxed(spicc->base + SPICC_STATREG)); in meson_spicc_rxready()
238 readl_relaxed(spicc->base + SPICC_RXDATA)); in meson_spicc_rx()
247 spicc->base + SPICC_TXDATA); in meson_spicc_tx()
266 spicc->base + SPICC_CONREG); in meson_spicc_setup_burst()
276 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); in meson_spicc_irq()
283 writel(0, spicc->base in meson_spicc_irq()
[all...]
H A Dspi-fsl-qspi.c189 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
419 void __iomem *base = q->iobase; in fsl_qspi_prepare_lut() local
465 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); in fsl_qspi_prepare_lut()
562 void __iomem *base = q->iobase; in fsl_qspi_fill_txfifo() local
569 qspi_writel(q, val, base + QUADSPI_TBDR); in fsl_qspi_fill_txfifo()
575 qspi_writel(q, val, base + QUADSPI_TBDR); in fsl_qspi_fill_txfifo()
580 qspi_writel(q, 0, base + QUADSPI_TBDR); in fsl_qspi_fill_txfifo()
587 void __iomem *base = q->iobase; in fsl_qspi_read_rxfifo() local
593 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); in fsl_qspi_read_rxfifo()
599 val = qspi_readl(q, base in fsl_qspi_read_rxfifo()
607 void __iomem *base = q->iobase; fsl_qspi_do_op() local
630 fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, u32 mask, u32 delay_us, u32 timeout_us) fsl_qspi_readl_poll_tout() argument
645 void __iomem *base = q->iobase; fsl_qspi_exec_op() local
723 void __iomem *base = q->iobase; fsl_qspi_default_setup() local
[all...]
H A Dspi-sprd.c152 void __iomem *base; member
200 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, in sprd_spi_wait_for_tx_end()
207 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val, in sprd_spi_wait_for_tx_end()
214 writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR); in sprd_spi_wait_for_tx_end()
225 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, in sprd_spi_wait_for_rx_end()
232 writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR); in sprd_spi_wait_for_rx_end()
239 writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12); in sprd_spi_tx_req()
244 writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12); in sprd_spi_rx_req()
249 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1); in sprd_spi_enter_idle()
252 writel_relaxed(val, ss->base in sprd_spi_enter_idle()
[all...]
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dsdhci_am654.c143 struct regmap *base; member
176 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, in sdhci_am654_setup_dll()
197 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); in sdhci_am654_setup_dll()
208 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, in sdhci_am654_setup_dll()
218 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); in sdhci_am654_setup_dll()
221 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, in sdhci_am654_setup_dll()
227 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, in sdhci_am654_setup_dll()
239 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_am654_write_itapdly()
241 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, in sdhci_am654_write_itapdly()
243 regmap_update_bits(sdhci_am654->base, PHY_CTRL in sdhci_am654_write_itapdly()
784 void __iomem *base; sdhci_am654_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-fsl-qspi.c188 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
418 void __iomem *base = q->iobase; in fsl_qspi_prepare_lut() local
464 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); in fsl_qspi_prepare_lut()
561 void __iomem *base = q->iobase; in fsl_qspi_fill_txfifo() local
568 qspi_writel(q, val, base + QUADSPI_TBDR); in fsl_qspi_fill_txfifo()
574 qspi_writel(q, val, base + QUADSPI_TBDR); in fsl_qspi_fill_txfifo()
579 qspi_writel(q, 0, base + QUADSPI_TBDR); in fsl_qspi_fill_txfifo()
586 void __iomem *base = q->iobase; in fsl_qspi_read_rxfifo() local
592 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); in fsl_qspi_read_rxfifo()
598 val = qspi_readl(q, base in fsl_qspi_read_rxfifo()
606 void __iomem *base = q->iobase; fsl_qspi_do_op() local
629 fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, u32 mask, u32 delay_us, u32 timeout_us) fsl_qspi_readl_poll_tout() argument
644 void __iomem *base = q->iobase; fsl_qspi_exec_op() local
722 void __iomem *base = q->iobase; fsl_qspi_default_setup() local
[all...]
H A Dspi-meson-spicc.c156 void __iomem *base; member
199 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | in meson_spicc_oen_enable()
202 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); in meson_spicc_oen_enable()
208 readl_relaxed(spicc->base + SPICC_STATREG)); in meson_spicc_txfull()
214 readl_relaxed(spicc->base + SPICC_STATREG)); in meson_spicc_rxready()
256 readl_relaxed(spicc->base + SPICC_RXDATA)); in meson_spicc_rx()
265 spicc->base + SPICC_TXDATA); in meson_spicc_tx()
284 spicc->base + SPICC_CONREG); in meson_spicc_setup_burst()
294 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); in meson_spicc_irq()
301 writel(0, spicc->base in meson_spicc_irq()
[all...]
H A Dspi-sprd.c151 void __iomem *base; member
199 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, in sprd_spi_wait_for_tx_end()
206 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val, in sprd_spi_wait_for_tx_end()
213 writel_relaxed(SPRD_SPI_TX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR); in sprd_spi_wait_for_tx_end()
224 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val, in sprd_spi_wait_for_rx_end()
231 writel_relaxed(SPRD_SPI_RX_END_INT_CLR, ss->base + SPRD_SPI_INT_CLR); in sprd_spi_wait_for_rx_end()
238 writel_relaxed(SPRD_SPI_SW_TX_REQ, ss->base + SPRD_SPI_CTL12); in sprd_spi_tx_req()
243 writel_relaxed(SPRD_SPI_SW_RX_REQ, ss->base + SPRD_SPI_CTL12); in sprd_spi_rx_req()
248 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1); in sprd_spi_enter_idle()
251 writel_relaxed(val, ss->base in sprd_spi_enter_idle()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_mem_input_v.c46 mem_input110->base.ctx, in set_flip_control()
54 mem_input110->base.ctx, in set_flip_control()
75 mem_input110->base.ctx, in program_pri_addr_c()
89 mem_input110->base.ctx, in program_pri_addr_c()
111 mem_input110->base.ctx, in program_pri_addr_l()
125 mem_input110->base.ctx, in program_pri_addr_l()
158 value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE); in enable()
160 dm_write_reg(mem_input110->base.ctx, in enable()
203 mem_input110->base.ctx, in program_tiling()
225 mem_input110->base in program_tiling()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/dispnv50/
H A Dhead.c23 #include "base.h"
70 if (asyh->set.base ) head->func->base (head, asyh); in nv50_head_flush_set()
100 if (asyh->base.depth > asyh->or.bpc * 3) in nv50_head_atomic_check_dither()
228 struct drm_device *dev = head->base.base.dev; in nv50_head_atomic_check_lut()
229 struct drm_crtc *crtc = &head->base.base; in nv50_head_atomic_check_lut()
241 size, crtc->base.id, crtc->name); in nv50_head_atomic_check_lut()
273 size, crtc->base in nv50_head_atomic_check_lut()
574 struct nv50_wndw *base, *ovly, *curs; nv50_head_create() local
[all...]
/third_party/node/deps/v8/src/compiler/
H A Dheap-refs.h8 #include "src/base/optional.h"
195 static base::Optional<RefType> AsOptionalRef(JSHeapBroker* broker, in AsOptionalRef()
196 base::Optional<TinyRef<T>> ref) { in AsOptionalRef()
245 base::Optional<bool> TryGetBooleanValue() const;
254 return base::hash_combine(ref.object().address()); in operator ()()
300 using Flags = base::Flags<Flag>;
344 base::Optional<MapRef> map_direct_read() const;
381 base::Optional<ObjectRef> raw_properties_or_hash() const;
387 base::Optional<ObjectRef> RawInobjectPropertyAt(FieldIndex index) const;
393 base
[all...]
/kernel/linux/linux-5.10/crypto/
H A Dcryptd.c248 rctx->complete(&req->base, err); in cryptd_skcipher_complete()
255 static void cryptd_skcipher_encrypt(struct crypto_async_request *base, in cryptd_skcipher_encrypt() argument
258 struct skcipher_request *req = skcipher_request_cast(base); in cryptd_skcipher_encrypt()
277 req->base.complete = rctx->complete; in cryptd_skcipher_encrypt()
283 static void cryptd_skcipher_decrypt(struct crypto_async_request *base, in cryptd_skcipher_decrypt() argument
286 struct skcipher_request *req = skcipher_request_cast(base); in cryptd_skcipher_decrypt()
305 req->base.complete = rctx->complete; in cryptd_skcipher_decrypt()
319 rctx->complete = req->base.complete; in cryptd_skcipher_enqueue()
320 req->base.complete = compl; in cryptd_skcipher_enqueue()
322 return cryptd_enqueue_request(queue, &req->base); in cryptd_skcipher_enqueue()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
158 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_link_train()
194 ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000); in gt215_link_train()
237 ram->base.func->calc(&ram->base, clk_current); in gt215_link_train()
246 ram_train_result(ram->base.fb, result, 64); in gt215_link_train()
281 struct nvkm_device *device = ram->base in gt215_link_train_init()
492 gt215_ram_calc(struct nvkm_ram *base, u32 freq) gt215_ram_calc() argument
883 gt215_ram_prog(struct nvkm_ram *base) gt215_ram_prog() argument
908 gt215_ram_tidy(struct nvkm_ram *base) gt215_ram_tidy() argument
915 gt215_ram_init(struct nvkm_ram *base) gt215_ram_init() argument
923 gt215_ram_dtor(struct nvkm_ram *base) gt215_ram_dtor() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramgt215.c25 #define gt215_ram(p) container_of((p), struct gt215_ram, base)
39 struct ramfuc base; member
94 struct nvkm_ram base; member
158 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in gt215_link_train()
194 ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000); in gt215_link_train()
237 ram->base.func->calc(&ram->base, clk_current); in gt215_link_train()
246 ram_train_result(ram->base.fb, result, 64); in gt215_link_train()
281 struct nvkm_device *device = ram->base in gt215_link_train_init()
492 gt215_ram_calc(struct nvkm_ram *base, u32 freq) gt215_ram_calc() argument
883 gt215_ram_prog(struct nvkm_ram *base) gt215_ram_prog() argument
908 gt215_ram_tidy(struct nvkm_ram *base) gt215_ram_tidy() argument
915 gt215_ram_init(struct nvkm_ram *base) gt215_ram_init() argument
923 gt215_ram_dtor(struct nvkm_ram *base) gt215_ram_dtor() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_display.c289 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_wait_for_pipe_off()
333 struct drm_i915_private *i915 = to_i915(plane->base.dev); in assert_plane()
341 plane->base.name, str_on_off(state), in assert_plane()
350 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in assert_planes_disabled()
364 switch (dig_port->base.port) { in vlv_wait_port_ready()
366 MISSING_CASE(dig_port->base.port); in vlv_wait_port_ready()
387 dig_port->base.base.base.id, dig_port->base in vlv_wait_port_ready()
[all...]
/kernel/linux/linux-6.6/drivers/crypto/stm32/
H A Dstm32-cryp.c1238 base); in stm32_cryp_cipher_one_req()
1253 base); in stm32_cryp_aead_one_req()
1685 .base = {
1686 .base.cra_name = "ecb(aes)",
1687 .base.cra_driver_name = "stm32-ecb-aes",
1688 .base.cra_priority = 200,
1689 .base.cra_flags = CRYPTO_ALG_ASYNC,
1690 .base.cra_blocksize = AES_BLOCK_SIZE,
1691 .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1692 .base
[all...]
/kernel/linux/linux-5.10/drivers/crypto/allwinner/sun8i-ss/
H A Dsun8i-ss-hash.c54 crypto_tfm_alg_driver_name(&op->fallback_tfm->base)); in sun8i_ss_hash_crainit()
82 rctx->fallback_req.base.flags = areq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; in sun8i_ss_hash_init()
94 rctx->fallback_req.base.flags = areq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; in sun8i_ss_hash_export()
106 rctx->fallback_req.base.flags = areq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP; in sun8i_ss_hash_import()
117 struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); in sun8i_ss_hash_final()
122 rctx->fallback_req.base.flags = areq->base in sun8i_ss_hash_final()
[all...]
/kernel/linux/linux-5.10/drivers/i2c/busses/
H A Di2c-synquacer.c140 void __iomem *base; member
184 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); in synquacer_i2c_stop()
204 writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR); in synquacer_i2c_hw_init()
208 i2c->base + SYNQUACER_I2C_REG_FSR); in synquacer_i2c_hw_init()
223 i2c->base + SYNQUACER_I2C_REG_CCR); in synquacer_i2c_hw_init()
224 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); in synquacer_i2c_hw_init()
237 i2c->base + SYNQUACER_I2C_REG_CCR); in synquacer_i2c_hw_init()
238 writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR); in synquacer_i2c_hw_init()
245 writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR); in synquacer_i2c_hw_init()
246 writeb(0, i2c->base in synquacer_i2c_hw_init()
[all...]
/kernel/linux/linux-5.10/drivers/scsi/
H A Daha1740.c197 static int aha1740_test_port(unsigned int base) in aha1740_test_port() argument
199 if ( inb(PORTADR(base)) & PORTADDR_ENH ) in aha1740_test_port()
215 unsigned int base; in aha1740_intr_handle() local
224 base = host->io_port; in aha1740_intr_handle()
228 while(inb(G2STAT(base)) & G2STAT_INTPEND) { in aha1740_intr_handle()
231 adapstat = inb(G2INTST(base)); in aha1740_intr_handle()
232 ecbptr = ecb_dma_to_cpu (host, inl(MBOXIN0(base))); in aha1740_intr_handle()
233 outb(G2CNTRL_IRST,G2CNTRL(base)); /* interrupt reset */ in aha1740_intr_handle()
240 outb(G2CNTRL_HRDY,G2CNTRL(base)); in aha1740_intr_handle()
243 inb(G2STAT(base)),adapsta in aha1740_intr_handle()
457 unsigned int base = SCpnt->device->host->io_port; aha1740_queuecommand_lck() local
492 aha1740_getconfig(unsigned int base, unsigned int *irq_level, unsigned int *irq_type, unsigned int *translation) aha1740_getconfig() argument
[all...]
/kernel/linux/linux-5.10/drivers/usb/usbip/
H A Dusbip_common.c262 pdu->base.command, in usbip_dump_header()
263 pdu->base.seqnum, in usbip_dump_header()
264 pdu->base.devid, in usbip_dump_header()
265 pdu->base.direction, in usbip_dump_header()
266 pdu->base.ep); in usbip_dump_header()
268 switch (pdu->base.command) { in usbip_dump_header()
415 static void correct_endian_basic(struct usbip_header_basic *base, int send) in correct_endian_basic() argument
418 base->command = cpu_to_be32(base->command); in correct_endian_basic()
419 base in correct_endian_basic()
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