Lines Matching refs:base
189 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
419 void __iomem *base = q->iobase;
465 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
562 void __iomem *base = q->iobase;
569 qspi_writel(q, val, base + QUADSPI_TBDR);
575 qspi_writel(q, val, base + QUADSPI_TBDR);
580 qspi_writel(q, 0, base + QUADSPI_TBDR);
587 void __iomem *base = q->iobase;
593 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
599 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
607 void __iomem *base = q->iobase;
618 base + QUADSPI_IPCR);
630 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
638 return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
645 void __iomem *base = q->iobase;
653 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
663 base + QUADSPI_SFAR);
665 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
667 base + QUADSPI_MCR);
670 base + QUADSPI_SPTRCLR);
672 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
673 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
674 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
688 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
723 void __iomem *base = q->iobase;
741 base + QUADSPI_MCR);
746 base + QUADSPI_MCR);
754 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
756 base + QUADSPI_FLSHCR);
758 reg = qspi_readl(q, base + QUADSPI_SMPR);
762 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
765 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
766 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
767 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
771 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
774 base + QUADSPI_BUF3CR);
787 base + QUADSPI_SFA1AD);
789 base + QUADSPI_SFA2AD);
791 base + QUADSPI_SFB1AD);
793 base + QUADSPI_SFB2AD);
799 base + QUADSPI_MCR);