Lines Matching refs:base
188 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory)
418 void __iomem *base = q->iobase;
464 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i));
561 void __iomem *base = q->iobase;
568 qspi_writel(q, val, base + QUADSPI_TBDR);
574 qspi_writel(q, val, base + QUADSPI_TBDR);
579 qspi_writel(q, 0, base + QUADSPI_TBDR);
586 void __iomem *base = q->iobase;
592 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
598 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4));
606 void __iomem *base = q->iobase;
617 base + QUADSPI_IPCR);
629 static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base,
637 return readl_poll_timeout(base, reg, !(reg & mask), delay_us,
644 void __iomem *base = q->iobase;
652 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK |
662 base + QUADSPI_SFAR);
664 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
666 base + QUADSPI_MCR);
669 base + QUADSPI_SPTRCLR);
671 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
672 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
673 qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
687 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT);
722 void __iomem *base = q->iobase;
740 base + QUADSPI_MCR);
745 base + QUADSPI_MCR);
753 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
755 base + QUADSPI_FLSHCR);
757 reg = qspi_readl(q, base + QUADSPI_SMPR);
761 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
764 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
765 qspi_writel(q, 0, base + QUADSPI_BUF1IND);
766 qspi_writel(q, 0, base + QUADSPI_BUF2IND);
770 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT);
773 base + QUADSPI_BUF3CR);
786 base + QUADSPI_SFA1AD);
788 base + QUADSPI_SFA2AD);
790 base + QUADSPI_SFB1AD);
792 base + QUADSPI_SFB2AD);
798 base + QUADSPI_MCR);