Lines Matching refs:base
143 struct regmap *base;
176 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
197 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
208 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
218 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
221 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
227 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
239 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
241 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
243 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
251 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
255 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
270 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
296 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
303 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
325 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
327 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
429 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
637 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
640 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
643 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
645 ret = regmap_read_poll_timeout(sdhci_am654->base,
656 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
663 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
667 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
784 void __iomem *base;
812 base = devm_platform_ioremap_resource(pdev, 1);
813 if (IS_ERR(base)) {
814 ret = PTR_ERR(base);
818 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
820 if (IS_ERR(sdhci_am654->base)) {
822 ret = PTR_ERR(sdhci_am654->base);
897 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
900 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
902 ret = regmap_read_poll_timeout(sdhci_am654->base,
913 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
920 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
923 regmap_read(sdhci_am654->base, CTL_CFG_3, &val);
926 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,