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/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-hibvt.c38 void __iomem *base; member
71 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, in hibvt_pwm_set_bits() argument
74 void __iomem *address = base + offset; in hibvt_pwm_set_bits()
87 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
95 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
110 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
113 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
124 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
127 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
135 void __iomem *base; in hibvt_pwm_get_state() local
[all...]
H A Dpwm-microchip-core.c59 void __iomem *base; member
85 channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset); in mchp_core_pwm_enable()
89 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset); in mchp_core_pwm_enable()
181 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
182 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm)); in mchp_core_pwm_apply_duty()
317 hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); in mchp_core_pwm_apply_locked()
318 hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD); in mchp_core_pwm_apply_locked()
349 writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE); in mchp_core_pwm_apply_locked()
350 writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD); in mchp_core_pwm_apply_locked()
409 prescale = readb_relaxed(mchp_core_pwm->base in mchp_core_pwm_get_state()
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/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-apple-nco.c35 * The REG_DIV register indirectly expresses a base integer divisor, roughly
37 * base divisor is adjusted on a cycle-by-cycle basis based on the state of a
68 void __iomem *base; member
82 val = readl_relaxed(chan->base + REG_CTRL); in applnco_enable_nolock()
83 writel_relaxed(val | CTRL_ENABLE, chan->base + REG_CTRL); in applnco_enable_nolock()
91 val = readl_relaxed(chan->base + REG_CTRL); in applnco_disable_nolock()
92 writel_relaxed(val & ~CTRL_ENABLE, chan->base + REG_CTRL); in applnco_disable_nolock()
99 return (readl_relaxed(chan->base + REG_CTRL) & CTRL_ENABLE) != 0; in applnco_is_enabled()
175 writel_relaxed(div, chan->base + REG_DIV); in applnco_set_rate()
176 writel_relaxed(inc1, chan->base in applnco_set_rate()
261 void __iomem *base; applnco_probe() local
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/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-sun5i.c37 void __iomem *base; member
60 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1)); in sun5i_clkevt_sync()
62 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS) in sun5i_clkevt_sync()
68 u32 val = readl(ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
69 writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_stop()
76 writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); in sun5i_clkevt_time_setup()
81 u32 val = readl(ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
89 ce->base + TIMER_CTL_REG(timer)); in sun5i_clkevt_time_start()
135 writel(0x1, ce->base + TIMER_IRQ_ST_REG); in sun5i_timer_interrupt()
145 return ~readl(cs->base in sun5i_clksrc_read()
176 void __iomem *base = cs->base; sun5i_setup_clocksource() local
203 void __iomem *base = ce->base; sun5i_setup_clockevent() local
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/kernel/linux/linux-6.6/drivers/crypto/inside-secure/
H A Dsafexcel_ring.c23 cdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
26 if (!cdr->base) in safexcel_init_ring_descriptors()
28 cdr->write = cdr->base; in safexcel_init_ring_descriptors()
29 cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1); in safexcel_init_ring_descriptors()
30 cdr->read = cdr->base; in safexcel_init_ring_descriptors()
48 cdesc = cdr->base; in safexcel_init_ring_descriptors()
60 rdr->base = dmam_alloc_coherent(priv->dev, in safexcel_init_ring_descriptors()
63 if (!rdr->base) in safexcel_init_ring_descriptors()
65 rdr->write = rdr->base; in safexcel_init_ring_descriptors()
66 rdr->base_end = rdr->base in safexcel_init_ring_descriptors()
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/kernel/linux/linux-6.6/drivers/input/touchscreen/
H A Dsun4i-ts.c109 void __iomem *base; member
122 x = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
123 y = readl(ts->base + TP_DATA); in sun4i_ts_irq_handle_input()
152 reg_val = readl(ts->base + TP_INT_FIFOS); in sun4i_ts_irq()
155 ts->temp_data = readl(ts->base + TEMP_DATA); in sun4i_ts_irq()
160 writel(reg_val, ts->base + TP_INT_FIFOS); in sun4i_ts_irq()
171 TP_UP_IRQ_EN(1), ts->base + TP_INT_FIFOC); in sun4i_ts_open()
181 writel(TEMP_IRQ_EN(1), ts->base + TP_INT_FIFOC); in sun4i_ts_close()
304 ts->base = devm_platform_ioremap_resource(pdev, 0); in sun4i_ts_probe()
305 if (IS_ERR(ts->base)) in sun4i_ts_probe()
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/kernel/linux/linux-6.6/sound/soc/xilinx/
H A Dxlnx_spdif.c50 void __iomem *base; member
60 val = readl(ctx->base + XSPDIF_IRQ_STS_REG); in xlnx_spdifrx_irq_handler()
63 ctx->base + XSPDIF_IRQ_STS_REG); in xlnx_spdifrx_irq_handler()
64 val = readl(ctx->base + in xlnx_spdifrx_irq_handler()
67 ctx->base + XSPDIF_IRQ_ENABLE_REG); in xlnx_spdifrx_irq_handler()
83 val = readl(ctx->base + XSPDIF_CONTROL_REG); in xlnx_spdif_startup()
85 writel(val, ctx->base + XSPDIF_CONTROL_REG); in xlnx_spdif_startup()
89 ctx->base + XSPDIF_IRQ_ENABLE_REG); in xlnx_spdif_startup()
91 ctx->base + XSPDIF_GLOBAL_IRQ_ENABLE_REG); in xlnx_spdif_startup()
102 writel(XSPDIF_SOFT_RESET_VALUE, ctx->base in xlnx_spdif_shutdown()
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/third_party/mesa3d/src/egl/drivers/dri2/
H A Dplatform_surfaceless.c46 dri2_surf->base.Width, in surfaceless_alloc_image()
47 dri2_surf->base.Height, in surfaceless_alloc_image()
57 dri2_egl_display(dri2_surf->base.Resource.Display); in surfaceless_free_images()
78 dri2_egl_display(dri2_surf->base.Resource.Display); in surfaceless_image_get_buffers()
130 if (!dri2_init_surface(&dri2_surf->base, disp, type, conf, attrib_list, in dri2_surfaceless_create_surface()
135 dri2_surf->base.GLColorspace); in dri2_surfaceless_create_surface()
149 return &dri2_surf->base; in dri2_surfaceless_create_surface()
204 .base = { __DRI_KOPPER_LOADER, 1 },
210 .base = { __DRI_IMAGE_LOADER, 2 },
217 &image_loader_extension.base,
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/third_party/node/deps/v8/src/libplatform/tracing/
H A Dtracing-controller.cc10 #include "src/base/atomicops.h"
11 #include "src/base/platform/mutex.h"
12 #include "src/base/platform/time.h"
13 #include "src/base/platform/wrappers.h"
22 #include "src/base/platform/platform.h"
23 #include "src/base/platform/semaphore.h"
70 v8::base::AtomicWord g_category_index = g_num_builtin_categories;
73 TracingController::TracingController() { mutex_.reset(new base::Mutex()); } in TracingController()
81 base::MutexGuard lock(mutex_.get()); in ~TracingController()
109 return base in CurrentTimestampMicroseconds()
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/base/security/crypto_framework/plugin/openssl_plugin/key/asy_key_generator/src/
H A Ddsa_asy_key_generator_openssl.c36 HcfAsyKeyGeneratorSpi base; member
135 DestroyDsaPubKey((HcfObjectBase *)impl->base.pubKey); in DestroyDsaKeyPair()
136 impl->base.pubKey = NULL; in DestroyDsaKeyPair()
137 DestroyDsaPriKey((HcfObjectBase *)impl->base.priKey); in DestroyDsaKeyPair()
138 impl->base.priKey = NULL; in DestroyDsaKeyPair()
434 pk->base.base.base.destroy = DestroyDsaPubKey; in FillOpensslDsaPubKeyFunc()
435 pk->base.base in FillOpensslDsaPubKeyFunc()
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/third_party/mesa3d/src/gallium/drivers/v3d/
H A Dv3d_program.c106 v3d_get_slot_for_driver_location(so->base.ir.nir, output->register_index); in v3d_set_transform_feedback_outputs()
162 so->base.stream_output.stride[buffer] = in v3d_set_transform_feedback_outputs()
167 so->tf_outputs = ralloc_array(so->base.ir.nir, struct v3d_varying_slot, in v3d_set_transform_feedback_outputs()
208 nir_shader *s = so->base.ir.nir; in v3d_shader_precompile()
212 .base.shader_state = so, in v3d_shader_precompile()
226 v3d_setup_shared_precompile_key(so, &key.base); in v3d_shader_precompile()
227 v3d_get_compiled_shader(v3d, &key.base, sizeof(key)); in v3d_shader_precompile()
230 .base.shader_state = so, in v3d_shader_precompile()
231 .base.is_last_geometry_stage = true, in v3d_shader_precompile()
234 v3d_setup_shared_precompile_key(so, &key.base); in v3d_shader_precompile()
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/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
H A Dnv84_video.c136 assert(target->base.buffer_format == PIPE_FORMAT_NV12); in nv84_decoder_decode_bitstream_h264()
193 align(0x20 * mb(dec->base.width) * mb(dec->base.height), 0x100); in nv84_decoder_begin_frame_mpeg12()
268 struct nouveau_screen *screen = &nv50->screen->base; in nv84_create_decoder()
297 dec->base = *templ; in nv84_create_decoder()
298 dec->base.context = context; in nv84_create_decoder()
299 dec->base.destroy = nv84_decoder_destroy; in nv84_create_decoder()
300 dec->base.flush = nv84_decoder_flush; in nv84_create_decoder()
302 dec->base.decode_bitstream = nv84_decoder_decode_bitstream_h264; in nv84_create_decoder()
303 dec->base in nv84_create_decoder()
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/third_party/node/deps/v8/src/trap-handler/
H A Dhandler-inside.cc53 const uintptr_t base = data->base; in TryFindLandingPad() local
55 if (fault_addr >= base && fault_addr < base + data->size) { in TryFindLandingPad()
57 const uint32_t offset = static_cast<uint32_t>(fault_addr - base); in TryFindLandingPad()
60 TH_DCHECK(base + offset == fault_addr); in TryFindLandingPad()
65 *landing_pad = data->instructions[j].landing_offset + base; in TryFindLandingPad()
/third_party/mesa3d/src/util/
H A Du_qsort.h35 void util_tls_qsort_r(void *base, size_t nmemb, size_t size,
55 util_qsort_r(void *base, size_t nmemb, size_t size, in util_qsort_r() argument
68 qsort_r(base, nmemb, size, &data, util_qsort_adapter); in util_qsort_r()
71 qsort_r(base, nmemb, size, compar, arg); in util_qsort_r()
82 qsort_s(base, nmemb, size, util_qsort_adapter, &data); in util_qsort_r()
85 qsort_s(base, nmemb, size, compar, arg); in util_qsort_r()
89 util_tls_qsort_r(base, nmemb, size, compar, arg); in util_qsort_r()
/third_party/skia/third_party/externals/sfntly/java/src/com/google/typography/font/sfntly/table/opentype/component/
H A DRangeRecord.java15 RangeRecord(ReadableFontData data, int base) { in RangeRecord() argument
16 this.start = data.readUShort(base + START_OFFSET); in RangeRecord()
17 this.end = data.readUShort(base + END_OFFSET); in RangeRecord()
18 this.property = data.readUShort(base + PROPERTY_OFFSET); in RangeRecord()
22 public int writeTo(WritableFontData newData, int base) { in writeTo() argument
23 newData.writeUShort(base + START_OFFSET, start); in writeTo()
24 newData.writeUShort(base + END_OFFSET, end); in writeTo()
/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-mxc.c61 void __iomem *base; member
180 void __iomem *reg = port->base; in gpio_set_irq_type()
216 val = readl(port->base + GPIO_EDGE_SEL); in gpio_set_irq_type()
219 port->base + GPIO_EDGE_SEL); in gpio_set_irq_type()
222 port->base + GPIO_EDGE_SEL); in gpio_set_irq_type()
232 writel(1 << gpio_idx, port->base + GPIO_ISR); in gpio_set_irq_type()
239 void __iomem *reg = port->base; in mxc_flip_edge()
286 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); in mx3_gpio_irq_handler()
304 irq_msk = readl(port->base in mx2_gpio_irq_handler()
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/kernel/linux/linux-5.10/drivers/mmc/host/
H A Dsdhci_am654.c142 struct regmap *base; member
175 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, in sdhci_am654_setup_dll()
196 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); in sdhci_am654_setup_dll()
207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, in sdhci_am654_setup_dll()
217 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); in sdhci_am654_setup_dll()
220 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, in sdhci_am654_setup_dll()
226 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, in sdhci_am654_setup_dll()
238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_am654_write_itapdly()
240 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, in sdhci_am654_write_itapdly()
242 regmap_update_bits(sdhci_am654->base, PHY_CTRL in sdhci_am654_write_itapdly()
774 void __iomem *base; sdhci_am654_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-mxc.c61 void __iomem *base; member
168 void __iomem *reg = port->base; in gpio_set_irq_type()
206 val = readl(port->base + GPIO_EDGE_SEL); in gpio_set_irq_type()
209 port->base + GPIO_EDGE_SEL); in gpio_set_irq_type()
212 port->base + GPIO_EDGE_SEL); in gpio_set_irq_type()
222 writel(1 << gpio_idx, port->base + GPIO_ISR); in gpio_set_irq_type()
232 void __iomem *reg = port->base; in mxc_flip_edge()
288 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); in mx3_gpio_irq_handler()
306 irq_msk = readl(port->base in mx2_gpio_irq_handler()
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/kernel/linux/linux-6.6/drivers/media/platform/qcom/camss/
H A Dcamss-csiphy-3ph-1-0.c272 csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); in csiphy_hw_version_read()
274 hw_version = readl_relaxed(csiphy->base + in csiphy_hw_version_read()
276 hw_version |= readl_relaxed(csiphy->base + in csiphy_hw_version_read()
278 hw_version |= readl_relaxed(csiphy->base + in csiphy_hw_version_read()
280 hw_version |= readl_relaxed(csiphy->base + in csiphy_hw_version_read()
292 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); in csiphy_reset()
294 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); in csiphy_reset()
304 u8 val = readl_relaxed(csiphy->base + in csiphy_isr()
307 writel_relaxed(val, csiphy->base + in csiphy_isr()
311 writel_relaxed(0x1, csiphy->base in csiphy_isr()
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/third_party/mesa3d/src/imagination/vulkan/winsys/pvrsrvkm/
H A Dpvr_srv.c76 result = pvr_winsys_helper_winsys_heap_init(&srv_ws->base, in pvr_srv_heap_init()
83 &srv_heap->base); in pvr_srv_heap_init()
87 assert(srv_heap->base.page_size == srv_ws->base.page_size); in pvr_srv_heap_init()
88 assert(srv_heap->base.log2_page_size == srv_ws->base.log2_page_size); in pvr_srv_heap_init()
89 assert(srv_heap->base.reserved_size % PVR_SRV_RESERVED_SIZE_GRANULARITY == in pvr_srv_heap_init()
94 srv_heap->base.base_addr, in pvr_srv_heap_init()
95 srv_heap->base.size, in pvr_srv_heap_init()
96 srv_heap->base in pvr_srv_heap_init()
[all...]
/base/security/crypto_framework/test/unittest/src/
H A Dcrypto_x25519_asy_key_generator_by_spec_test.cpp94 const char *className = returnObj->base.getClass(); in HWTEST_F()
109 returnObj->base.destroy((HcfObjectBase *)returnObj); in HWTEST_F()
162 const char *className = keyPair->base.getClass(); in HWTEST_F()
183 keyPair->base.destroy(&(keyPair->base)); in HWTEST_F()
202 const char *className = keyPair->pubKey->base.base.getClass(); in HWTEST_F()
223 keyPair->pubKey->base.base.destroy(&(keyPair->pubKey->base in HWTEST_F()
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/kernel/linux/linux-5.10/drivers/mtd/nand/onenand/
H A Donenand_samsung.c126 void __iomem *base; member
147 return readl(onenand->base + offset); in s3c_read_reg()
152 writel(value, onenand->base + offset); in s3c_write_reg()
172 (unsigned int) onenand->base + i, in s3c_dump_reg()
220 int reg = addr - this->base; in s3c_onenand_readw()
270 unsigned int reg = addr - this->base; in s3c_onenand_writew()
519 void __iomem *base = onenand->dma_addr; in s5pc110_dma_poll() local
523 writel(src, base + S5PC110_DMA_SRC_ADDR); in s5pc110_dma_poll()
524 writel(dst, base + S5PC110_DMA_DST_ADDR); in s5pc110_dma_poll()
527 writel(S5PC110_DMA_SRC_CFG_READ, base in s5pc110_dma_poll()
563 void __iomem *base = onenand->dma_addr; s5pc110_onenand_irq() local
585 void __iomem *base = onenand->dma_addr; s5pc110_dma_irq() local
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/kernel/linux/linux-5.10/drivers/pinctrl/
H A Dpinctrl-amd.c46 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
62 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
64 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
78 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
84 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
97 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
110 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
115 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
132 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_set_debounce()
137 pin_reg = readl(gpio_dev->base in amd_gpio_set_debounce()
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/kernel/linux/linux-5.10/drivers/phy/qualcomm/
H A Dphy-qcom-qusb2.c324 * @base: iomapped memory space for qubs2 phy
344 void __iomem *base; member
363 static inline void qusb2_write_mask(void __iomem *base, u32 offset, in qusb2_write_mask() argument
368 reg = readl(base + offset); in qusb2_write_mask()
371 writel(reg, base + offset); in qusb2_write_mask()
374 readl(base + offset); in qusb2_write_mask()
377 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) in qusb2_setbits() argument
381 reg = readl(base + offset); in qusb2_setbits()
383 writel(reg, base + offset); in qusb2_setbits()
386 readl(base in qusb2_setbits()
389 qusb2_clrbits(void __iomem *base, u32 offset, u32 val) qusb2_clrbits() argument
402 qcom_qusb2_phy_configure(void __iomem *base, const unsigned int *regs, const struct qusb2_phy_init_tbl tbl[], int num) qcom_qusb2_phy_configure() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h88 struct drm_framebuffer base; member
129 struct drm_encoder base; member
186 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
418 struct drm_connector base; member
456 struct drm_connector_state base; member
462 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
477 struct drm_atomic_state base; member
593 u32 base; member
1105 struct drm_crtc base; member
1155 struct drm_plane base; member
1164 u32 base, cntl, size; global() member
1407 struct intel_encoder base; global() member
1450 struct intel_encoder base; global() member
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