Lines Matching refs:base
59 void __iomem *base;
85 channel_enable = readb_relaxed(mchp_core_pwm->base + reg_offset);
89 writel_relaxed(channel_enable, mchp_core_pwm->base + reg_offset);
181 writel_relaxed(posedge, mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
182 writel_relaxed(negedge, mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
317 hw_prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
318 hw_period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
349 writel_relaxed(prescale, mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
350 writel_relaxed(period_steps, mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
409 prescale = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PRESCALE);
410 period_steps = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_PERIOD);
416 posedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_POSEDGE(pwm->hwpwm));
417 negedge = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_NEGEDGE(pwm->hwpwm));
459 mchp_core_pwm->base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
460 if (IS_ERR(mchp_core_pwm->base))
461 return PTR_ERR(mchp_core_pwm->base);
478 mchp_core_pwm->channel_enabled = readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(0));
480 readb_relaxed(mchp_core_pwm->base + MCHPCOREPWM_EN(1)) << 8;
486 writel_relaxed(1U, mchp_core_pwm->base + MCHPCOREPWM_SYNC_UPD);