Lines Matching refs:base
142 struct regmap *base;
175 regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
196 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK,
217 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
220 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
226 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val,
238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK,
240 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK,
242 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0);
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
254 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
269 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
295 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
302 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
324 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
326 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
428 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
639 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
642 regmap_read(sdhci_am654->base, PHY_STAT1, &val);
645 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
647 ret = regmap_read_poll_timeout(sdhci_am654->base,
658 regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
665 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
669 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK,
774 void __iomem *base;
810 base = devm_platform_ioremap_resource(pdev, 1);
811 if (IS_ERR(base)) {
812 ret = PTR_ERR(base);
816 sdhci_am654->base = devm_regmap_init_mmio(dev, base,
818 if (IS_ERR(sdhci_am654->base)) {
820 ret = PTR_ERR(sdhci_am654->base);