1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/kernel.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/module.h>
13 #include <linux/nvmem-consumer.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
24
25 #define QUSB2PHY_PLL_TEST 0x04
26 #define CLK_REF_SEL BIT(7)
27
28 #define QUSB2PHY_PLL_TUNE 0x08
29 #define QUSB2PHY_PLL_USER_CTL1 0x0c
30 #define QUSB2PHY_PLL_USER_CTL2 0x10
31 #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
32 #define QUSB2PHY_PLL_PWR_CTRL 0x18
33
34 /* QUSB2PHY_PLL_STATUS register bits */
35 #define PLL_LOCKED BIT(5)
36
37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
38 #define CORE_READY_STATUS BIT(0)
39
40 /* QUSB2PHY_PORT_POWERDOWN register bits */
41 #define CLAMP_N_EN BIT(5)
42 #define FREEZIO_N BIT(1)
43 #define POWER_DOWN BIT(0)
44
45 /* QUSB2PHY_PWR_CTRL1 register bits */
46 #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
47 #define PWR_CTRL1_CLAMP_N_EN BIT(1)
48
49 #define QUSB2PHY_REFCLK_ENABLE BIT(0)
50
51 #define PHY_CLK_SCHEME_SEL BIT(0)
52
53 /* QUSB2PHY_INTR_CTRL register bits */
54 #define DMSE_INTR_HIGH_SEL BIT(4)
55 #define DPSE_INTR_HIGH_SEL BIT(3)
56 #define CHG_DET_INTR_EN BIT(2)
57 #define DMSE_INTR_EN BIT(1)
58 #define DPSE_INTR_EN BIT(0)
59
60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
61 #define CORE_PLL_EN_FROM_RESET BIT(4)
62 #define CORE_RESET BIT(5)
63 #define CORE_RESET_MUX BIT(6)
64
65 /* QUSB2PHY_IMP_CTRL1 register bits */
66 #define IMP_RES_OFFSET_MASK GENMASK(5, 0)
67 #define IMP_RES_OFFSET_SHIFT 0x0
68
69 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
70 #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
71 #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
72
73 /* QUSB2PHY_CHG_CONTROL_2 register bits */
74 #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
75 #define CHG_CTRL2_OFFSET_SHIFT 0x4
76
77 /* QUSB2PHY_PORT_TUNE1 register bits */
78 #define HSTX_TRIM_MASK GENMASK(7, 4)
79 #define HSTX_TRIM_SHIFT 0x4
80 #define PREEMPH_WIDTH_HALF_BIT BIT(2)
81 #define PREEMPHASIS_EN_MASK GENMASK(1, 0)
82 #define PREEMPHASIS_EN_SHIFT 0x0
83
84 /* QUSB2PHY_PORT_TUNE2 register bits */
85 #define HSDISC_TRIM_MASK GENMASK(1, 0)
86 #define HSDISC_TRIM_SHIFT 0x0
87
88 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
89 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
90 #define QUSB2PHY_PLL_CMODE 0x2c
91 #define QUSB2PHY_PLL_LOCK_DELAY 0x184
92 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
93 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
94 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
95 #define QUSB2PHY_PWR_CTRL2 0x214
96 #define QUSB2PHY_IMP_CTRL1 0x220
97 #define QUSB2PHY_IMP_CTRL2 0x224
98 #define QUSB2PHY_CHG_CTRL2 0x23c
99
100 struct qusb2_phy_init_tbl {
101 unsigned int offset;
102 unsigned int val;
103 /*
104 * register part of layout ?
105 * if yes, then offset gives index in the reg-layout
106 */
107 int in_layout;
108 };
109
110 #define QUSB2_PHY_INIT_CFG(o, v) \
111 { \
112 .offset = o, \
113 .val = v, \
114 }
115
116 #define QUSB2_PHY_INIT_CFG_L(o, v) \
117 { \
118 .offset = o, \
119 .val = v, \
120 .in_layout = 1, \
121 }
122
123 /* set of registers with offsets different per-PHY */
124 enum qusb2phy_reg_layout {
125 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
126 QUSB2PHY_PLL_STATUS,
127 QUSB2PHY_PORT_TUNE1,
128 QUSB2PHY_PORT_TUNE2,
129 QUSB2PHY_PORT_TUNE3,
130 QUSB2PHY_PORT_TUNE4,
131 QUSB2PHY_PORT_TUNE5,
132 QUSB2PHY_PORT_TEST1,
133 QUSB2PHY_PORT_TEST2,
134 QUSB2PHY_PORT_POWERDOWN,
135 QUSB2PHY_INTR_CTRL,
136 };
137
138 static const unsigned int msm8996_regs_layout[] = {
139 [QUSB2PHY_PLL_STATUS] = 0x38,
140 [QUSB2PHY_PORT_TUNE1] = 0x80,
141 [QUSB2PHY_PORT_TUNE2] = 0x84,
142 [QUSB2PHY_PORT_TUNE3] = 0x88,
143 [QUSB2PHY_PORT_TUNE4] = 0x8c,
144 [QUSB2PHY_PORT_TUNE5] = 0x90,
145 [QUSB2PHY_PORT_TEST1] = 0xb8,
146 [QUSB2PHY_PORT_TEST2] = 0x9c,
147 [QUSB2PHY_PORT_POWERDOWN] = 0xb4,
148 [QUSB2PHY_INTR_CTRL] = 0xbc,
149 };
150
151 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
152 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
153 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
154 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
155 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
156
157 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
158 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
159 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
160
161 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
162
163 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
164 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
165 };
166
167 static const unsigned int msm8998_regs_layout[] = {
168 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
169 [QUSB2PHY_PLL_STATUS] = 0x1a0,
170 [QUSB2PHY_PORT_TUNE1] = 0x23c,
171 [QUSB2PHY_PORT_TUNE2] = 0x240,
172 [QUSB2PHY_PORT_TUNE3] = 0x244,
173 [QUSB2PHY_PORT_TUNE4] = 0x248,
174 [QUSB2PHY_PORT_TEST1] = 0x24c,
175 [QUSB2PHY_PORT_TEST2] = 0x250,
176 [QUSB2PHY_PORT_POWERDOWN] = 0x210,
177 [QUSB2PHY_INTR_CTRL] = 0x22c,
178 };
179
180 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
181 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
182 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
183 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
184 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
185
186 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
187 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
188
189 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
190 };
191
192 static const unsigned int qusb2_v2_regs_layout[] = {
193 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
194 [QUSB2PHY_PLL_STATUS] = 0x1a0,
195 [QUSB2PHY_PORT_TUNE1] = 0x240,
196 [QUSB2PHY_PORT_TUNE2] = 0x244,
197 [QUSB2PHY_PORT_TUNE3] = 0x248,
198 [QUSB2PHY_PORT_TUNE4] = 0x24c,
199 [QUSB2PHY_PORT_TUNE5] = 0x250,
200 [QUSB2PHY_PORT_TEST1] = 0x254,
201 [QUSB2PHY_PORT_TEST2] = 0x258,
202 [QUSB2PHY_PORT_POWERDOWN] = 0x210,
203 [QUSB2PHY_INTR_CTRL] = 0x230,
204 };
205
206 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
207 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
208 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
209 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
210 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
211 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
212 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
213 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
214 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
215 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
216 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
217
218 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
219 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
220 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
221 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
222 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
223
224 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
225 };
226
227 struct qusb2_phy_cfg {
228 const struct qusb2_phy_init_tbl *tbl;
229 /* number of entries in the table */
230 unsigned int tbl_num;
231 /* offset to PHY_CLK_SCHEME register in TCSR map */
232 unsigned int clk_scheme_offset;
233
234 /* array of registers with different offsets */
235 const unsigned int *regs;
236 unsigned int mask_core_ready;
237 unsigned int disable_ctrl;
238 unsigned int autoresume_en;
239
240 /* true if PHY has PLL_TEST register to select clk_scheme */
241 bool has_pll_test;
242
243 /* true if TUNE1 register must be updated by fused value, else TUNE2 */
244 bool update_tune1_with_efuse;
245
246 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
247 bool has_pll_override;
248 };
249
250 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
251 .tbl = msm8996_init_tbl,
252 .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
253 .regs = msm8996_regs_layout,
254
255 .has_pll_test = true,
256 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
257 .mask_core_ready = PLL_LOCKED,
258 .autoresume_en = BIT(3),
259 };
260
261 static const struct qusb2_phy_cfg msm8998_phy_cfg = {
262 .tbl = msm8998_init_tbl,
263 .tbl_num = ARRAY_SIZE(msm8998_init_tbl),
264 .regs = msm8998_regs_layout,
265
266 .disable_ctrl = POWER_DOWN,
267 .mask_core_ready = CORE_READY_STATUS,
268 .has_pll_override = true,
269 .autoresume_en = BIT(0),
270 .update_tune1_with_efuse = true,
271 };
272
273 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
274 .tbl = qusb2_v2_init_tbl,
275 .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
276 .regs = qusb2_v2_regs_layout,
277
278 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
279 POWER_DOWN),
280 .mask_core_ready = CORE_READY_STATUS,
281 .has_pll_override = true,
282 .autoresume_en = BIT(0),
283 .update_tune1_with_efuse = true,
284 };
285
286 static const char * const qusb2_phy_vreg_names[] = {
287 "vdda-pll", "vdda-phy-dpdm",
288 };
289
290 #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names)
291
292 /* struct override_param - structure holding qusb2 v2 phy overriding param
293 * set override true if the device tree property exists and read and assign
294 * to value
295 */
296 struct override_param {
297 bool override;
298 u8 value;
299 };
300
301 /*struct override_params - structure holding qusb2 v2 phy overriding params
302 * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
303 * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register
304 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
305 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
306 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
307 * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
308 * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register
309 */
310 struct override_params {
311 struct override_param imp_res_offset;
312 struct override_param hstx_trim;
313 struct override_param preemphasis;
314 struct override_param preemphasis_width;
315 struct override_param bias_ctrl;
316 struct override_param charge_ctrl;
317 struct override_param hsdisc_trim;
318 };
319
320 /**
321 * struct qusb2_phy - structure holding qusb2 phy attributes
322 *
323 * @phy: generic phy
324 * @base: iomapped memory space for qubs2 phy
325 *
326 * @cfg_ahb_clk: AHB2PHY interface clock
327 * @ref_clk: phy reference clock
328 * @iface_clk: phy interface clock
329 * @phy_reset: phy reset control
330 * @vregs: regulator supplies bulk data
331 *
332 * @tcsr: TCSR syscon register map
333 * @cell: nvmem cell containing phy tuning value
334 *
335 * @overrides: pointer to structure for all overriding tuning params
336 *
337 * @cfg: phy config data
338 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
339 * @phy_initialized: indicate if PHY has been initialized
340 * @mode: current PHY mode
341 */
342 struct qusb2_phy {
343 struct phy *phy;
344 void __iomem *base;
345
346 struct clk *cfg_ahb_clk;
347 struct clk *ref_clk;
348 struct clk *iface_clk;
349 struct reset_control *phy_reset;
350 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
351
352 struct regmap *tcsr;
353 struct nvmem_cell *cell;
354
355 struct override_params overrides;
356
357 const struct qusb2_phy_cfg *cfg;
358 bool has_se_clk_scheme;
359 bool phy_initialized;
360 enum phy_mode mode;
361 };
362
qusb2_write_mask(void __iomem *base, u32 offset, u32 val, u32 mask)363 static inline void qusb2_write_mask(void __iomem *base, u32 offset,
364 u32 val, u32 mask)
365 {
366 u32 reg;
367
368 reg = readl(base + offset);
369 reg &= ~mask;
370 reg |= val & mask;
371 writel(reg, base + offset);
372
373 /* Ensure above write is completed */
374 readl(base + offset);
375 }
376
qusb2_setbits(void __iomem *base, u32 offset, u32 val)377 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
378 {
379 u32 reg;
380
381 reg = readl(base + offset);
382 reg |= val;
383 writel(reg, base + offset);
384
385 /* Ensure above write is completed */
386 readl(base + offset);
387 }
388
qusb2_clrbits(void __iomem *base, u32 offset, u32 val)389 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
390 {
391 u32 reg;
392
393 reg = readl(base + offset);
394 reg &= ~val;
395 writel(reg, base + offset);
396
397 /* Ensure above write is completed */
398 readl(base + offset);
399 }
400
401 static inline
qcom_qusb2_phy_configure(void __iomem *base, const unsigned int *regs, const struct qusb2_phy_init_tbl tbl[], int num)402 void qcom_qusb2_phy_configure(void __iomem *base,
403 const unsigned int *regs,
404 const struct qusb2_phy_init_tbl tbl[], int num)
405 {
406 int i;
407
408 for (i = 0; i < num; i++) {
409 if (tbl[i].in_layout)
410 writel(tbl[i].val, base + regs[tbl[i].offset]);
411 else
412 writel(tbl[i].val, base + tbl[i].offset);
413 }
414 }
415
416 /*
417 * Update board specific PHY tuning override values if specified from
418 * device tree.
419 */
qusb2_phy_override_phy_params(struct qusb2_phy *qphy)420 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
421 {
422 const struct qusb2_phy_cfg *cfg = qphy->cfg;
423 struct override_params *or = &qphy->overrides;
424
425 if (or->imp_res_offset.override)
426 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
427 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
428 IMP_RES_OFFSET_MASK);
429
430 if (or->bias_ctrl.override)
431 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
432 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
433 BIAS_CTRL2_RES_OFFSET_MASK);
434
435 if (or->charge_ctrl.override)
436 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
437 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
438 CHG_CTRL2_OFFSET_MASK);
439
440 if (or->hstx_trim.override)
441 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
442 or->hstx_trim.value << HSTX_TRIM_SHIFT,
443 HSTX_TRIM_MASK);
444
445 if (or->preemphasis.override)
446 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
447 or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
448 PREEMPHASIS_EN_MASK);
449
450 if (or->preemphasis_width.override) {
451 if (or->preemphasis_width.value ==
452 QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
453 qusb2_setbits(qphy->base,
454 cfg->regs[QUSB2PHY_PORT_TUNE1],
455 PREEMPH_WIDTH_HALF_BIT);
456 else
457 qusb2_clrbits(qphy->base,
458 cfg->regs[QUSB2PHY_PORT_TUNE1],
459 PREEMPH_WIDTH_HALF_BIT);
460 }
461
462 if (or->hsdisc_trim.override)
463 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
464 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
465 HSDISC_TRIM_MASK);
466 }
467
468 /*
469 * Fetches HS Tx tuning value from nvmem and sets the
470 * QUSB2PHY_PORT_TUNE1/2 register.
471 * For error case, skip setting the value and use the default value.
472 */
qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)473 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
474 {
475 struct device *dev = &qphy->phy->dev;
476 const struct qusb2_phy_cfg *cfg = qphy->cfg;
477 u8 *val, hstx_trim;
478
479 /* efuse register is optional */
480 if (!qphy->cell)
481 return;
482
483 /*
484 * Read efuse register having TUNE2/1 parameter's high nibble.
485 * If efuse register shows value as 0x0 (indicating value is not
486 * fused), or if we fail to find a valid efuse register setting,
487 * then use default value for high nibble that we have already
488 * set while configuring the phy.
489 */
490 val = nvmem_cell_read(qphy->cell, NULL);
491 if (IS_ERR(val)) {
492 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
493 return;
494 }
495 hstx_trim = val[0];
496 kfree(val);
497 if (!hstx_trim) {
498 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
499 return;
500 }
501
502 /* Fused TUNE1/2 value is the higher nibble only */
503 if (cfg->update_tune1_with_efuse)
504 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
505 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
506 else
507 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
508 hstx_trim << HSTX_TRIM_SHIFT, HSTX_TRIM_MASK);
509 }
510
qusb2_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)511 static int qusb2_phy_set_mode(struct phy *phy,
512 enum phy_mode mode, int submode)
513 {
514 struct qusb2_phy *qphy = phy_get_drvdata(phy);
515
516 qphy->mode = mode;
517
518 return 0;
519 }
520
qusb2_phy_runtime_suspend(struct device *dev)521 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
522 {
523 struct qusb2_phy *qphy = dev_get_drvdata(dev);
524 const struct qusb2_phy_cfg *cfg = qphy->cfg;
525 u32 intr_mask;
526
527 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
528
529 if (!qphy->phy_initialized) {
530 dev_vdbg(dev, "PHY not initialized, bailing out\n");
531 return 0;
532 }
533
534 /*
535 * Enable DP/DM interrupts to detect line state changes based on current
536 * speed. In other words, enable the triggers _opposite_ of what the
537 * current D+/D- levels are e.g. if currently D+ high, D- low
538 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
539 */
540 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
541 switch (qphy->mode) {
542 case PHY_MODE_USB_HOST_HS:
543 case PHY_MODE_USB_HOST_FS:
544 case PHY_MODE_USB_DEVICE_HS:
545 case PHY_MODE_USB_DEVICE_FS:
546 intr_mask |= DMSE_INTR_HIGH_SEL;
547 break;
548 case PHY_MODE_USB_HOST_LS:
549 case PHY_MODE_USB_DEVICE_LS:
550 intr_mask |= DPSE_INTR_HIGH_SEL;
551 break;
552 default:
553 /* No device connected, enable both DP/DM high interrupt */
554 intr_mask |= DMSE_INTR_HIGH_SEL;
555 intr_mask |= DPSE_INTR_HIGH_SEL;
556 break;
557 }
558
559 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
560
561 /* hold core PLL into reset */
562 if (cfg->has_pll_override) {
563 qusb2_setbits(qphy->base,
564 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
565 CORE_PLL_EN_FROM_RESET | CORE_RESET |
566 CORE_RESET_MUX);
567 }
568
569 /* enable phy auto-resume only if device is connected on bus */
570 if (qphy->mode != PHY_MODE_INVALID) {
571 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
572 cfg->autoresume_en);
573 /* Autoresume bit has to be toggled in order to enable it */
574 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
575 cfg->autoresume_en);
576 }
577
578 if (!qphy->has_se_clk_scheme)
579 clk_disable_unprepare(qphy->ref_clk);
580
581 clk_disable_unprepare(qphy->cfg_ahb_clk);
582 clk_disable_unprepare(qphy->iface_clk);
583
584 return 0;
585 }
586
qusb2_phy_runtime_resume(struct device *dev)587 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
588 {
589 struct qusb2_phy *qphy = dev_get_drvdata(dev);
590 const struct qusb2_phy_cfg *cfg = qphy->cfg;
591 int ret;
592
593 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
594
595 if (!qphy->phy_initialized) {
596 dev_vdbg(dev, "PHY not initialized, bailing out\n");
597 return 0;
598 }
599
600 ret = clk_prepare_enable(qphy->iface_clk);
601 if (ret) {
602 dev_err(dev, "failed to enable iface_clk, %d\n", ret);
603 return ret;
604 }
605
606 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
607 if (ret) {
608 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
609 goto disable_iface_clk;
610 }
611
612 if (!qphy->has_se_clk_scheme) {
613 ret = clk_prepare_enable(qphy->ref_clk);
614 if (ret) {
615 dev_err(dev, "failed to enable ref clk, %d\n", ret);
616 goto disable_ahb_clk;
617 }
618 }
619
620 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
621
622 /* bring core PLL out of reset */
623 if (cfg->has_pll_override) {
624 qusb2_clrbits(qphy->base,
625 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
626 CORE_RESET | CORE_RESET_MUX);
627 }
628
629 return 0;
630
631 disable_ahb_clk:
632 clk_disable_unprepare(qphy->cfg_ahb_clk);
633 disable_iface_clk:
634 clk_disable_unprepare(qphy->iface_clk);
635
636 return ret;
637 }
638
qusb2_phy_init(struct phy *phy)639 static int qusb2_phy_init(struct phy *phy)
640 {
641 struct qusb2_phy *qphy = phy_get_drvdata(phy);
642 const struct qusb2_phy_cfg *cfg = qphy->cfg;
643 unsigned int val = 0;
644 unsigned int clk_scheme;
645 int ret;
646
647 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
648
649 /* turn on regulator supplies */
650 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
651 if (ret)
652 return ret;
653
654 ret = clk_prepare_enable(qphy->iface_clk);
655 if (ret) {
656 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
657 goto poweroff_phy;
658 }
659
660 /* enable ahb interface clock to program phy */
661 ret = clk_prepare_enable(qphy->cfg_ahb_clk);
662 if (ret) {
663 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
664 goto disable_iface_clk;
665 }
666
667 /* Perform phy reset */
668 ret = reset_control_assert(qphy->phy_reset);
669 if (ret) {
670 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
671 goto disable_ahb_clk;
672 }
673
674 /* 100 us delay to keep PHY in reset mode */
675 usleep_range(100, 150);
676
677 ret = reset_control_deassert(qphy->phy_reset);
678 if (ret) {
679 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
680 goto disable_ahb_clk;
681 }
682
683 /* Disable the PHY */
684 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
685 qphy->cfg->disable_ctrl);
686
687 if (cfg->has_pll_test) {
688 /* save reset value to override reference clock scheme later */
689 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
690 }
691
692 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
693 cfg->tbl_num);
694
695 /* Override board specific PHY tuning values */
696 qusb2_phy_override_phy_params(qphy);
697
698 /* Set efuse value for tuning the PHY */
699 qusb2_phy_set_tune2_param(qphy);
700
701 /* Enable the PHY */
702 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
703 POWER_DOWN);
704
705 /* Required to get phy pll lock successfully */
706 usleep_range(150, 160);
707
708 /* Default is single-ended clock on msm8996 */
709 qphy->has_se_clk_scheme = true;
710 /*
711 * read TCSR_PHY_CLK_SCHEME register to check if single-ended
712 * clock scheme is selected. If yes, then disable differential
713 * ref_clk and use single-ended clock, otherwise use differential
714 * ref_clk only.
715 */
716 if (qphy->tcsr) {
717 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
718 &clk_scheme);
719 if (ret) {
720 dev_err(&phy->dev, "failed to read clk scheme reg\n");
721 goto assert_phy_reset;
722 }
723
724 /* is it a differential clock scheme ? */
725 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
726 dev_vdbg(&phy->dev, "%s(): select differential clk\n",
727 __func__);
728 qphy->has_se_clk_scheme = false;
729 } else {
730 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
731 __func__);
732 }
733 }
734
735 if (!qphy->has_se_clk_scheme) {
736 ret = clk_prepare_enable(qphy->ref_clk);
737 if (ret) {
738 dev_err(&phy->dev, "failed to enable ref clk, %d\n",
739 ret);
740 goto assert_phy_reset;
741 }
742 }
743
744 if (cfg->has_pll_test) {
745 if (!qphy->has_se_clk_scheme)
746 val &= ~CLK_REF_SEL;
747 else
748 val |= CLK_REF_SEL;
749
750 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
751
752 /* ensure above write is through */
753 readl(qphy->base + QUSB2PHY_PLL_TEST);
754 }
755
756 /* Required to get phy pll lock successfully */
757 usleep_range(100, 110);
758
759 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
760 if (!(val & cfg->mask_core_ready)) {
761 dev_err(&phy->dev,
762 "QUSB2PHY pll lock failed: status reg = %x\n", val);
763 ret = -EBUSY;
764 goto disable_ref_clk;
765 }
766 qphy->phy_initialized = true;
767
768 return 0;
769
770 disable_ref_clk:
771 if (!qphy->has_se_clk_scheme)
772 clk_disable_unprepare(qphy->ref_clk);
773 assert_phy_reset:
774 reset_control_assert(qphy->phy_reset);
775 disable_ahb_clk:
776 clk_disable_unprepare(qphy->cfg_ahb_clk);
777 disable_iface_clk:
778 clk_disable_unprepare(qphy->iface_clk);
779 poweroff_phy:
780 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
781
782 return ret;
783 }
784
qusb2_phy_exit(struct phy *phy)785 static int qusb2_phy_exit(struct phy *phy)
786 {
787 struct qusb2_phy *qphy = phy_get_drvdata(phy);
788
789 /* Disable the PHY */
790 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
791 qphy->cfg->disable_ctrl);
792
793 if (!qphy->has_se_clk_scheme)
794 clk_disable_unprepare(qphy->ref_clk);
795
796 reset_control_assert(qphy->phy_reset);
797
798 clk_disable_unprepare(qphy->cfg_ahb_clk);
799 clk_disable_unprepare(qphy->iface_clk);
800
801 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
802
803 qphy->phy_initialized = false;
804
805 return 0;
806 }
807
808 static const struct phy_ops qusb2_phy_gen_ops = {
809 .init = qusb2_phy_init,
810 .exit = qusb2_phy_exit,
811 .set_mode = qusb2_phy_set_mode,
812 .owner = THIS_MODULE,
813 };
814
815 static const struct of_device_id qusb2_phy_of_match_table[] = {
816 {
817 .compatible = "qcom,ipq8074-qusb2-phy",
818 .data = &msm8996_phy_cfg,
819 }, {
820 .compatible = "qcom,msm8996-qusb2-phy",
821 .data = &msm8996_phy_cfg,
822 }, {
823 .compatible = "qcom,msm8998-qusb2-phy",
824 .data = &msm8998_phy_cfg,
825 }, {
826 /*
827 * Deprecated. Only here to support legacy device
828 * trees that didn't include "qcom,qusb2-v2-phy"
829 */
830 .compatible = "qcom,sdm845-qusb2-phy",
831 .data = &qusb2_v2_phy_cfg,
832 }, {
833 .compatible = "qcom,qusb2-v2-phy",
834 .data = &qusb2_v2_phy_cfg,
835 },
836 { },
837 };
838 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
839
840 static const struct dev_pm_ops qusb2_phy_pm_ops = {
841 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
842 qusb2_phy_runtime_resume, NULL)
843 };
844
qusb2_phy_probe(struct platform_device *pdev)845 static int qusb2_phy_probe(struct platform_device *pdev)
846 {
847 struct device *dev = &pdev->dev;
848 struct qusb2_phy *qphy;
849 struct phy_provider *phy_provider;
850 struct phy *generic_phy;
851 struct resource *res;
852 int ret, i;
853 int num;
854 u32 value;
855 struct override_params *or;
856
857 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
858 if (!qphy)
859 return -ENOMEM;
860 or = &qphy->overrides;
861
862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
863 qphy->base = devm_ioremap_resource(dev, res);
864 if (IS_ERR(qphy->base))
865 return PTR_ERR(qphy->base);
866
867 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
868 if (IS_ERR(qphy->cfg_ahb_clk)) {
869 ret = PTR_ERR(qphy->cfg_ahb_clk);
870 if (ret != -EPROBE_DEFER)
871 dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
872 return ret;
873 }
874
875 qphy->ref_clk = devm_clk_get(dev, "ref");
876 if (IS_ERR(qphy->ref_clk)) {
877 ret = PTR_ERR(qphy->ref_clk);
878 if (ret != -EPROBE_DEFER)
879 dev_err(dev, "failed to get ref clk, %d\n", ret);
880 return ret;
881 }
882
883 qphy->iface_clk = devm_clk_get_optional(dev, "iface");
884 if (IS_ERR(qphy->iface_clk))
885 return PTR_ERR(qphy->iface_clk);
886
887 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
888 if (IS_ERR(qphy->phy_reset)) {
889 dev_err(dev, "failed to get phy core reset\n");
890 return PTR_ERR(qphy->phy_reset);
891 }
892
893 num = ARRAY_SIZE(qphy->vregs);
894 for (i = 0; i < num; i++)
895 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
896
897 ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
898 if (ret) {
899 if (ret != -EPROBE_DEFER)
900 dev_err(dev, "failed to get regulator supplies: %d\n",
901 ret);
902 return ret;
903 }
904
905 /* Get the specific init parameters of QMP phy */
906 qphy->cfg = of_device_get_match_data(dev);
907
908 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
909 "qcom,tcsr-syscon");
910 if (IS_ERR(qphy->tcsr)) {
911 dev_dbg(dev, "failed to lookup TCSR regmap\n");
912 qphy->tcsr = NULL;
913 }
914
915 qphy->cell = devm_nvmem_cell_get(dev, NULL);
916 if (IS_ERR(qphy->cell)) {
917 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
918 return -EPROBE_DEFER;
919 qphy->cell = NULL;
920 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
921 }
922
923 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
924 &value)) {
925 or->imp_res_offset.value = (u8)value;
926 or->imp_res_offset.override = true;
927 }
928
929 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
930 &value)) {
931 or->bias_ctrl.value = (u8)value;
932 or->bias_ctrl.override = true;
933 }
934
935 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
936 &value)) {
937 or->charge_ctrl.value = (u8)value;
938 or->charge_ctrl.override = true;
939 }
940
941 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
942 &value)) {
943 or->hstx_trim.value = (u8)value;
944 or->hstx_trim.override = true;
945 }
946
947 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
948 &value)) {
949 or->preemphasis.value = (u8)value;
950 or->preemphasis.override = true;
951 }
952
953 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
954 &value)) {
955 or->preemphasis_width.value = (u8)value;
956 or->preemphasis_width.override = true;
957 }
958
959 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
960 &value)) {
961 or->hsdisc_trim.value = (u8)value;
962 or->hsdisc_trim.override = true;
963 }
964
965 pm_runtime_set_active(dev);
966 pm_runtime_enable(dev);
967 /*
968 * Prevent runtime pm from being ON by default. Users can enable
969 * it using power/control in sysfs.
970 */
971 pm_runtime_forbid(dev);
972
973 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
974 if (IS_ERR(generic_phy)) {
975 ret = PTR_ERR(generic_phy);
976 dev_err(dev, "failed to create phy, %d\n", ret);
977 pm_runtime_disable(dev);
978 return ret;
979 }
980 qphy->phy = generic_phy;
981
982 dev_set_drvdata(dev, qphy);
983 phy_set_drvdata(generic_phy, qphy);
984
985 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
986 if (!IS_ERR(phy_provider))
987 dev_info(dev, "Registered Qcom-QUSB2 phy\n");
988 else
989 pm_runtime_disable(dev);
990
991 return PTR_ERR_OR_ZERO(phy_provider);
992 }
993
994 static struct platform_driver qusb2_phy_driver = {
995 .probe = qusb2_phy_probe,
996 .driver = {
997 .name = "qcom-qusb2-phy",
998 .pm = &qusb2_phy_pm_ops,
999 .of_match_table = qusb2_phy_of_match_table,
1000 },
1001 };
1002
1003 module_platform_driver(qusb2_phy_driver);
1004
1005 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1006 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
1007 MODULE_LICENSE("GPL v2");
1008