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Searched defs:lane (Results 1 - 25 of 54) sorted by relevance

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/third_party/mesa3d/src/panfrost/bifrost/
H A Dbi_lower_divergent_indirects.c89 nir_ssa_def *lane = nir_load_subgroup_invocation(b); in bi_lower_divergent_indirects_impl() local
/foundation/arkui/ace_engine/frameworks/core/components_ng/pattern/waterflow/layout/sliding_window/
H A Dwater_flow_layout_info_sw.cpp72 const auto& lane = lanes_[GetSegment(itemIdx)][idxToLane_.at(itemIdx)]; in DistanceToTop() local
88 const auto& lane = lanes_[GetSegment(itemIdx)][idxToLane_.at(itemIdx)]; in DistanceToBottom() local
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H A Dwater_flow_layout_sw.cpp366 auto& lane = info_->lanes_[secIdx][laneIdx]; in FillBackHelper() local
378 auto& lane = info_->lanes_[secIdx][laneIdx]; FillFrontHelper() local
446 auto& lane = info_->lanes_[info_->GetSegment(i)][laneIdx]; ClearBack() local
469 auto& lane = info_->lanes_[info_->GetSegment(i)][laneIdx]; ClearFront() local
558 auto& lane = info_->lanes_[info_->GetSegment(jumpIdx)][0]; Jump() local
653 const auto& lane = info_->lanes_[idx][i]; LayoutSection() local
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/foundation/arkui/ace_engine/frameworks/core/components_v2/list/
H A Drosen_render_list_item_group.cpp62 size_t lane = 0; in PaintDivider() local
H A Drosen_render_list.cpp186 int lane = 0; in PaintDivider() local
/third_party/node/deps/base64/base64/lib/arch/neon32/
H A Ddec_loop.c25 dec_loop_neon32_lane (uint8x16_t *lane) in dec_loop_neon32_lane() argument
/third_party/mbedtls/library/
H A Dsha3.c103 uint64_t lane[5]; in keccak_f1600() local
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/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_lowering_gm107.cpp141 Value *lane = bld.mkImm(l); in handleManualTXD() local
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H A Dnv50_ir_emit_nv50.cpp841 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) in emitQUADOP() argument
/third_party/mesa3d/src/panfrost/bifrost/valhall/
H A Dvalhall.h79 bool lane : 1; member
/third_party/astc-encoder/Source/
H A Dastcenc_vecmathlib_none_4.h105 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
249 template <int l> ASTCENC_SIMD_INLINE int lane() const lane() function
357 template <int l> ASTCENC_SIMD_INLINE float lane() const lane() function
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H A Dastcenc_vecmathlib_avx2_8.h100 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
216 template <int l> ASTCENC_SIMD_INLINE int lane() const in lane() function
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H A Dastcenc_vecmathlib_sse_4.h100 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
260 template <int l> ASTCENC_SIMD_INLINE int lane() const in lane() function
382 template <int l> ASTCENC_SIMD_INLINE bool lane() const lane() function
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H A Dastcenc_vecmathlib_neon_4.h100 template <int l> ASTCENC_SIMD_INLINE float lane() const in lane() function
244 template <int l> ASTCENC_SIMD_INLINE int lane() const lane() function
362 template <int32_t l> ASTCENC_SIMD_INLINE bool lane() const lane() function
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/third_party/node/deps/v8/src/codegen/shared-ia32-x64/
H A Dmacro-assembler-shared-ia32-x64.cc132 F64x2ExtractLane(DoubleRegister dst, XMMRegister src, uint8_t lane) F64x2ExtractLane() argument
151 F64x2ReplaceLane(XMMRegister dst, XMMRegister src, DoubleRegister rep, uint8_t lane) F64x2ReplaceLane() argument
332 F32x4ExtractLane(FloatRegister dst, XMMRegister src, uint8_t lane) F32x4ExtractLane() argument
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/third_party/node/deps/v8/src/compiler/
H A Dint64-lowering.cc1040 int32_t lane = OpParameter<int32_t>(node->op()); in LowerNode() local
1048 int32_t lane = OpParameter<int32_t>(node->op()); in LowerNode() local
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc2053 int8_t lane = i.InputInt8(1); in AssembleArchInstruction() local
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/third_party/node/deps/v8/src/execution/s390/
H A Dsimulator-s390.h424 T get_simd_register_by_lane(int reg, int lane, in get_simd_register_by_lane() argument
437 set_simd_register_by_lane(int reg, int lane, const T& value, bool force_ibm_lane_numbering = true) set_simd_register_by_lane() argument
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/third_party/vixl/test/aarch64/
H A Dtest-utils-aarch64.cc358 EqualSVELane(uint64_t expected, const RegisterDump* core, const ZRegister& reg, int lane) EqualSVELane() argument
387 EqualSVELane(uint64_t expected, const RegisterDump* core, const PRegister& reg, int lane) EqualSVELane() argument
/third_party/python/Objects/
H A Dtupleobject.c328 Py_uhash_t lane = PyObject_Hash(item[i]); in tuplehash() local
/third_party/skia/include/private/
H A DSkVx.h572 auto lane = [&](size_t i) variable
/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dcode-generator-mips64.cc3426 unsigned lane = shuffle & 0xFF; in AssembleArchInstruction() local
/third_party/node/deps/v8/src/compiler/backend/ia32/
H A Dcode-generator-ia32.cc1975 int8_t lane = i.InputInt8(1); in AssembleArchInstruction() local
3056 uint8_t lane = lanes >> k; in AssembleArchInstruction() local
3068 uint8_t lane = lanes >> k; in AssembleArchInstruction() local
3171 uint8_t lane in AssembleArchInstruction() local
3186 uint8_t lane = i.InputUint8(1) & 0xf; AssembleArchInstruction() local
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/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dcode-generator-mips.cc3256 unsigned lane = shuffle & 0xFF; in AssembleArchInstruction() local
/third_party/node/deps/v8/src/codegen/arm64/
H A Dmacro-assembler-arm64.h1209 void St1(const VRegister& vt, int lane, const MemOperand& dst) { in St1() argument
1650 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { in Ld1() argument
1662 void Ld2(const VRegister& vt, const VRegister& vt2, int lane, in Ld2() argument
1676 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) Ld3() argument
1691 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) Ld4() argument
1715 St2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& dst) St2() argument
1720 St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) St3() argument
1725 St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) St4() argument
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