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Searched refs:tiled (Results 1 - 25 of 25) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c154 struct si_texture *tiled = ssrc->surface.is_linear ? sdst : ssrc; in si_sdma_v4_v5_copy_texture() local
155 struct si_texture *linear = tiled == ssrc ? sdst : ssrc; in si_sdma_v4_v5_copy_texture()
156 unsigned tiled_width = DIV_ROUND_UP(tiled->buffer.b.b.width0, tiled->surface.blk_w); in si_sdma_v4_v5_copy_texture()
157 unsigned tiled_height = DIV_ROUND_UP(tiled->buffer.b.b.height0, tiled->surface.blk_h); in si_sdma_v4_v5_copy_texture()
160 uint64_t tiled_address = tiled == ssrc ? src_address : dst_address; in si_sdma_v4_v5_copy_texture()
164 bool dcc = vi_dcc_enabled(tiled, 0) && is_v5; in si_sdma_v4_v5_copy_texture()
165 assert(tiled->buffer.b.b.depth0 == 1); in si_sdma_v4_v5_copy_texture()
181 (is_v5 ? 0 : tiled in si_sdma_v4_v5_copy_texture()
294 struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst; cik_sdma_copy_texture() local
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/third_party/mesa3d/src/panfrost/shared/test/
H A Dtest-tiling.cpp121 * Helper to build test cases for tiled texture access. This test suite compares
140 void *tiled = calloc(bpp, tiled_width * tiled_height);
149 panfrost_store_tiled_image(tiled, linear, rx, ry, rw, rh,
153 ((uint8_t *) tiled)[i] = (i & 0xFF);
156 panfrost_load_tiled_image(linear, tiled, rx, ry, rw, rh,
160 ref_access_tiled(ref, store ? linear : tiled, rx, ry, rw, rh,
164 EXPECT_EQ(memcmp(ref, tiled, bpp * tiled_width * tiled_height), 0);
169 free(tiled);
/third_party/mesa3d/src/asahi/lib/
H A Dtiling.h29 void agx_detile(void *tiled, void *linear,
33 void agx_tile(void *tiled, void *linear,
H A Dtiling.c98 pixel_t *tiled = _tiled; \
112 pixel_t *ptiled = &tiled[tile_base + y_offs + x_offs];\
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_formats.c696 VkFormatFeatureFlags2 linear = 0, tiled = 0, buffer = 0; in radv_physical_device_get_format_properties() local
703 out_properties->optimalTilingFeatures = tiled; in radv_physical_device_get_format_properties()
711 out_properties->optimalTilingFeatures = tiled; in radv_physical_device_get_format_properties()
741 tiled |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT | in radv_physical_device_get_format_properties()
763 tiled |= VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT; in radv_physical_device_get_format_properties()
764 tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT; in radv_physical_device_get_format_properties()
765 tiled |= VK_FORMAT_FEATURE_2_BLIT_SRC_BIT | VK_FORMAT_FEATURE_2_BLIT_DST_BIT; in radv_physical_device_get_format_properties()
766 tiled |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT; in radv_physical_device_get_format_properties()
769 tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT; in radv_physical_device_get_format_properties()
772 tiled | in radv_physical_device_get_format_properties()
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/third_party/mesa3d/src/gallium/drivers/v3d/
H A Dv3d_resource.c295 if (rsc->tiled) { in v3d_resource_transfer_map()
296 /* No direct mappings of tiled, since we need to manually in v3d_resource_transfer_map()
355 if (!rsc->tiled) { in v3d_texture_subdata()
360 /* Otherwise, map and store the texture data directly into the tiled in v3d_texture_subdata()
403 if (rsc->tiled) { in v3d_resource_modifier()
404 /* A shared tiled buffer should always be allocated as UIF, in v3d_resource_modifier()
587 if (!rsc->tiled) { in v3d_setup_slices()
767 /* Use a tiled layout if we can, for better 3D performance. */ in v3d_resource_create_with_modifiers()
804 rsc->tiled = should_tile; in v3d_resource_create_with_modifiers()
808 rsc->tiled in v3d_resource_create_with_modifiers()
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H A Dv3d_blit.c77 struct pipe_resource *tiled = NULL; in v3d_render_blit() local
82 if (!src->tiled && in v3d_render_blit()
102 tiled = ctx->screen->resource_create(ctx->screen, &tmpl); in v3d_render_blit()
103 if (!tiled) { in v3d_render_blit()
104 fprintf(stderr, "Failed to create tiled blit temp\n"); in v3d_render_blit()
108 tiled, 0, in v3d_render_blit()
113 info->src.resource = tiled; in v3d_render_blit()
126 pipe_resource_reference(&tiled, NULL); in v3d_render_blit()
561 * the NV12 format with BROADCOM_SAND_COL128 modifier to UIF tiled format.
604 * the NV12 format with BROADCOM_SAND_COL128 modifier to UIF tiled forma
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H A Dv3d_resource.h96 bool tiled; member
H A Dv3dx_state.c1146 * have to copy to a temporary tiled texture. in v3d_create_sampler_view()
1148 if (!rsc->tiled && !(prsc->target == PIPE_TEXTURE_1D || in v3d_create_sampler_view()
1178 assert(rsc->tiled); in v3d_create_sampler_view()
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_resource.c181 if (rsc->tiled) { in vc4_resource_transfer_map()
182 /* No direct mappings of tiled, since we need to manually in vc4_resource_transfer_map()
235 if (!rsc->tiled || in vc4_texture_subdata()
242 /* Otherwise, map and store the texture data directly into the tiled in vc4_texture_subdata()
276 if (rsc->tiled) in vc4_resource_modifier()
382 if (!rsc->tiled) { in vc4_setup_slices()
482 if (!rsc->tiled) { in get_resource_texture_format()
506 /* Use a tiled layout if we can, for better 3D performance. */ in vc4_resource_create_with_modifiers()
544 rsc->tiled = should_tile; in vc4_resource_create_with_modifiers()
548 rsc->tiled in vc4_resource_create_with_modifiers()
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H A Dvc4_resource.h58 bool tiled; member
H A Dvc4_blit.c314 if (src->tiled) in vc4_yuv_blit()
320 /* YUV blits always turn raster-order to tiled */ in vc4_yuv_blit()
322 assert(dst->tiled); in vc4_yuv_blit()
340 /* Create a renderable surface mapping the T-tiled shadow buffer. in vc4_yuv_blit()
/third_party/mesa3d/src/gallium/drivers/lima/
H A Dlima_resource.c228 res->tiled = should_tile; in _lima_resource_create_with_modifiers()
330 res->tiled = false; in lima_resource_from_handle()
333 res->tiled = true; in lima_resource_from_handle()
339 res->tiled = false; in lima_resource_from_handle()
348 if (res->tiled || in lima_resource_from_handle()
357 if (res->tiled && res->levels[0].stride != stride) { in lima_resource_from_handle()
358 fprintf(stderr, "tiled imported buffer has mismatching stride: %d (BO) != %d (expected)", in lima_resource_from_handle()
363 if (!res->tiled && (res->levels[0].stride % 8)) { in lima_resource_from_handle()
368 if (!res->tiled && res->levels[0].stride < stride) { in lima_resource_from_handle()
413 if (res->tiled) in lima_resource_get_handle()
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H A Dlima_resource.h59 bool tiled; member
H A Dlima_texture.c95 if (lima_res->tiled) in lima_texture_desc_set_res()
H A Dlima_job.c743 if (res->tiled) { in lima_pack_wb_zsbuf_reg()
778 if (res->tiled) { in lima_pack_wb_cbuf_reg()
/third_party/libdrm/omap/
H A Domap_drm.c212 bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height; in omap_bo_new_impl()
225 /* allocate a new (un-tiled) buffer object */
244 .tiled = { in omap_bo_new_tiled()
H A Domap_drm.h54 #define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */
61 /* tiled modes */
68 uint32_t bytes; /* (for non-tiled formats) */
72 } tiled; /* (for tiled formats) */ member
108 /* note: in case of tiled buffers, the user virtual size can be
/third_party/mesa3d/src/broadcom/vulkan/
H A Dv3dv_image.c135 if (!image->tiled) { in v3d_setup_slices()
212 image->alignment = image->tiled ? 4096 : image->cpp; in v3d_setup_slices()
329 image->tiled = tiling == VK_IMAGE_TILING_OPTIMAL || in create_image()
H A Dv3dv_private.h594 bool tiled; member
/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_gmem.c521 // know otherwise how to go from linear in sysmem to tiled in gmem. in emit_mem2gmem_surf()
523 // tiled in sysmem (and fixup sampler state to assume tiled).. this in emit_mem2gmem_surf()
632 bool tiled; in emit_gmem2mem_surf() local
653 tiled = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level); in emit_gmem2mem_surf()
657 COND(tiled, A5XX_RB_RESOLVE_CNTL_3_TILED)); in emit_gmem2mem_surf()
/third_party/mesa3d/src/amd/addrlib/src/gfx11/
H A Dgfx11addrlib.cpp1968 const BOOL_32 tiled = (pIn->swizzleMode != ADDR_SW_LINEAR) ? TRUE : FALSE;
1970 if (tiled)
2008 const BOOL_32 inTail = tiled && (pIn->mipId >= infoOut.firstMipIdInTail) ? TRUE : FALSE;
2066 tiled && (requestMipWidth <= infoOut.blockWidth / 2) && (requestMipHeight <= infoOut.blockHeight) ?
2995 * Internal function to calculate alignment for tiled surface
3035 * Internal function to calculate alignment for micro tiled surface
3120 * Internal function to calculate alignment for macro tiled surface
3352 * Internal function to calculate address from coord for tiled swizzle surface
3799 * Internal function to calculate address from coord for micro tiled swizzle surface
3865 * Internal function to calculate address from coord for macro tiled swizzl
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/third_party/astc-encoder/Source/
H A Dtinyexr.h166 int tiled; // tile format image member
211 // Properties for tiled format(`tiledesc`).
212 int tiled; member
253 unsigned char **images; // image[channels][pixels]. NULL if tiled format.
10504 if (version->tiled && attr_name.compare("tiles") == 0) { in ParseEXRHeader()
10867 if (exr_header->tiled) { in DecodeChunk()
11272 } else if (exr_header->tiled) { in DecodeEXRImage()
11568 if (exr_header.tiled) { in LoadEXRWithLayer()
11635 if (exr_header.tiled) { in LoadEXRWithLayer()
11742 // transfoer `tiled` fro
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/third_party/mesa3d/src/amd/addrlib/src/gfx10/
H A Dgfx10addrlib.cpp2364 const BOOL_32 tiled = (pIn->swizzleMode != ADDR_SW_LINEAR) ? TRUE : FALSE;
2366 if (tiled)
2404 const BOOL_32 inTail = tiled && (pIn->mipId >= infoOut.firstMipIdInTail) ? TRUE : FALSE;
2460 tiled && (requestMipWidth <= infoOut.blockWidth / 2) && (requestMipHeight <= infoOut.blockHeight) ?
3512 * Internal function to calculate alignment for tiled surface
3552 * Internal function to calculate alignment for micro tiled surface
3637 * Internal function to calculate alignment for macro tiled surface
3867 * Internal function to calculate address from coord for tiled swizzle surface
4371 * Internal function to calculate address from coord for micro tiled swizzle surface
4437 * Internal function to calculate address from coord for macro tiled swizzl
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/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_clear_blit.c1853 * Currently we fake support for tiled swapped formats and use the unswapped
1864 struct tu_native_format tiled = tu6_format_texture(format, TILE6_3); in is_swapped_format() local
1865 return linear.fmt != tiled.fmt || linear.swap != tiled.swap; in is_swapped_format()
3018 /* for unknown reasons blit event can't msaa resolve these formats when tiled in blit_can_resolve()

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