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Searched refs:post_divider (Results 1 - 25 of 41) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Drv730_dpm.c52 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local
64 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
67 post_divider = 1; in rv730_populate_sclk_value()
69 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
92 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
131 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local
142 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
145 post_divider = 1; in rv730_populate_mclk_value()
167 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
H A Drv6xx_dpm.c150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
154 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
173 if (step->post_divider == 1) in rv6xx_output_stepping()
176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
177 u32 hi_len = step->post_divider - 2 - lo_len; in rv6xx_output_stepping()
199 next.post_divider = cur->post_divider; in rv6xx_next_vco_step()
213 return (cur->post_divider > target->post_divider) in rv6xx_can_step_post_div()
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H A Drv6xx_dpm.h34 u32 post_divider; member
H A Dradeon_legacy_crtc.c742 uint32_t post_divider = 0; in radeon_set_pll() local
820 &reference_div, &post_divider); in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
834 post_divider); in radeon_set_pll()
H A Drv770_dpm.c324 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local
332 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
336 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()
501 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local
513 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
515 post_divider = 1; in rv770_populate_sclk_value()
517 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
539 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Drv730_dpm.c50 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local
62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
65 post_divider = 1; in rv730_populate_sclk_value()
67 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
90 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
129 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local
140 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
143 post_divider = 1; in rv730_populate_mclk_value()
165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
H A Drv6xx_dpm.c150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
152 step->post_divider = 1; in rv6xx_convert_clock_to_stepping()
154 step->vco_frequency = clock * step->post_divider; in rv6xx_convert_clock_to_stepping()
173 if (step->post_divider == 1) in rv6xx_output_stepping()
176 u32 lo_len = (step->post_divider - 2) / 2; in rv6xx_output_stepping()
177 u32 hi_len = step->post_divider - 2 - lo_len; in rv6xx_output_stepping()
199 next.post_divider = cur->post_divider; in rv6xx_next_vco_step()
213 return (cur->post_divider > target->post_divider) in rv6xx_can_step_post_div()
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H A Drv6xx_dpm.h34 u32 post_divider; member
H A Dradeon_legacy_crtc.c742 uint32_t post_divider = 0; in radeon_set_pll() local
820 &reference_div, &post_divider); in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
834 post_divider); in radeon_set_pll()
H A Drv770_dpm.c326 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
338 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()
503 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local
515 post_divider = (0x0f & (dividers.post_div >> 4)) + (0x0f & dividers.post_div) + 2; in rv770_populate_sclk_value()
517 post_divider = 1; in rv770_populate_sclk_value()
519 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
541 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c363 u8 *post_divider) in anx7625_calculate_m_n()
381 for (*post_divider = 1; in anx7625_calculate_m_n()
382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) in anx7625_calculate_m_n()
383 *post_divider += 1; in anx7625_calculate_m_n()
385 if (*post_divider > POST_DIVIDER_MAX) { in anx7625_calculate_m_n()
386 for (*post_divider = 1; in anx7625_calculate_m_n()
388 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) in anx7625_calculate_m_n()
389 *post_divider += 1; in anx7625_calculate_m_n()
391 if (*post_divider > POST_DIVIDER_MAX) { in anx7625_calculate_m_n()
392 DRM_ERROR("cannot find property post_divider( in anx7625_calculate_m_n()
360 anx7625_calculate_m_n(u32 pixelclock, unsigned long *m, unsigned long *n, u8 *post_divider) anx7625_calculate_m_n() argument
425 anx7625_odfc_config(struct anx7625_data *ctx, u8 post_divider) anx7625_odfc_config() argument
483 u8 post_divider = 0; anx7625_dsi_video_timing_config() local
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/kernel/linux/linux-5.10/drivers/video/fbdev/aty/
H A Dmach64_gx.c346 u32 post_divider; in aty_var_to_pll_18818() local
352 post_divider = 1; in aty_var_to_pll_18818()
363 post_divider *= 2; in aty_var_to_pll_18818()
374 switch (post_divider) { in aty_var_to_pll_18818()
394 pll->ics2595.post_divider = post_divider; in aty_var_to_pll_18818()
502 /* u32 post_divider; */ in aty_var_to_pll_1703()
560 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
620 /* u32 post_divider; */ in aty_var_to_pll_8398()
678 pll->ics2595.post_divider in aty_var_to_pll_8398()
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H A Dradeon_monitor.c200 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); in radeon_get_panel_info_BIOS()
207 pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); in radeon_get_panel_info_BIOS()
671 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; in radeon_fixup_panel_info()
677 (rinfo->panel_info.post_divider << 16), in radeon_fixup_panel_info()
H A Datyfb.h79 u32 post_divider; member
H A Daty128fb.c424 u32 post_divider; member
1343 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1381 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1397 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
H A Dradeonfb.h265 int post_divider; member
/kernel/linux/linux-6.6/drivers/video/fbdev/aty/
H A Dmach64_gx.c346 u32 post_divider; in aty_var_to_pll_18818() local
352 post_divider = 1; in aty_var_to_pll_18818()
361 post_divider *= 2; in aty_var_to_pll_18818()
372 switch (post_divider) { in aty_var_to_pll_18818()
392 pll->ics2595.post_divider = post_divider; in aty_var_to_pll_18818()
500 /* u32 post_divider; */ in aty_var_to_pll_1703()
558 pll->ics2595.post_divider = divider; /* fuer nix */ in aty_var_to_pll_1703()
618 /* u32 post_divider; */ in aty_var_to_pll_8398()
676 pll->ics2595.post_divider in aty_var_to_pll_8398()
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H A Dradeon_monitor.c200 rinfo->panel_info.post_divider = BIOS_IN8(tmp + 48); in radeon_get_panel_info_BIOS()
207 pr_debug("post_divider = %x\n", rinfo->panel_info.post_divider); in radeon_get_panel_info_BIOS()
669 rinfo->panel_info.post_divider = (ppll_divn >> 16) & 0x7; in radeon_fixup_panel_info()
675 (rinfo->panel_info.post_divider << 16), in radeon_fixup_panel_info()
H A Datyfb.h81 u32 post_divider; member
H A Daty128fb.c424 u32 post_divider; member
1343 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()
1381 pll->post_divider = post_dividers[i]; in aty128_var_to_pll()
1397 "vclk_per: %d\n", pll->post_divider, in aty128_var_to_pll()
H A Dradeonfb.h265 int post_divider; member
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c139 uint32_t post_divider, in calculate_fb_and_fractional_fb_divider()
146 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; in calculate_fb_and_fractional_fb_divider()
198 uint32_t post_divider, in calc_fb_divider_checking_tolerance()
211 post_divider, in calc_fb_divider_checking_tolerance()
222 ref_divider * post_divider * in calc_fb_divider_checking_tolerance()
240 pll_settings->pix_clk_post_divider = post_divider; in calc_fb_divider_checking_tolerance()
244 actual_calculated_clock_100hz * post_divider / 10; in calc_fb_divider_checking_tolerance()
260 uint32_t post_divider; in calc_pll_dividers_in_range() local
271 post_divider = max_post_divider; in calc_pll_dividers_in_range()
272 post_divider > in calc_pll_dividers_in_range()
135 calculate_fb_and_fractional_fb_divider( struct calc_pll_clock_source *calc_pll_cs, uint32_t target_pix_clk_100hz, uint32_t ref_divider, uint32_t post_divider, uint32_t *feedback_divider_param, uint32_t *fract_feedback_divider_param) calculate_fb_and_fractional_fb_divider() argument
194 calc_fb_divider_checking_tolerance( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t ref_divider, uint32_t post_divider, uint32_t tolerance) calc_fb_divider_checking_tolerance() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c120 * @post_divider: Post Divider (already known)
136 uint32_t post_divider, in calculate_fb_and_fractional_fb_divider()
143 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; in calculate_fb_and_fractional_fb_divider()
182 * @post_divider: Post Divider (already known)
195 uint32_t post_divider, in calc_fb_divider_checking_tolerance()
208 post_divider, in calc_fb_divider_checking_tolerance()
219 ref_divider * post_divider * in calc_fb_divider_checking_tolerance()
237 pll_settings->pix_clk_post_divider = post_divider; in calc_fb_divider_checking_tolerance()
241 div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); in calc_fb_divider_checking_tolerance()
257 uint32_t post_divider; in calc_pll_dividers_in_range() local
132 calculate_fb_and_fractional_fb_divider( struct calc_pll_clock_source *calc_pll_cs, uint32_t target_pix_clk_100hz, uint32_t ref_divider, uint32_t post_divider, uint32_t *feedback_divider_param, uint32_t *fract_feedback_divider_param) calculate_fb_and_fractional_fb_divider() argument
191 calc_fb_divider_checking_tolerance( struct calc_pll_clock_source *calc_pll_cs, struct pll_settings *pll_settings, uint32_t ref_divider, uint32_t post_divider, uint32_t tolerance) calc_fb_divider_checking_tolerance() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atombios.h49 u32 post_divider; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atombios.h49 u32 post_divider; member

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