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Searched refs:mcr (Results 1 - 25 of 294) sorted by relevance

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/kernel/linux/linux-5.10/arch/arm/mm/
H A D	proc-fa526.S	`39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 87 mcr p15, 0, r0, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 108 mcr p1 [all...]`
H A D	proc-arm926.S	`53 mcr p15, 0, r0, c1, c0, 0 @ disable caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 109 mcr p1 [all...]`
H A D	proc-mohawk.S	`44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 138 mcr p1 [all...]`
H A D	proc-arm1020.S	`69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 145 mcr p1 [all...]`
H A D	proc-arm925.S	`84 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 mcr p15, 0, ip, c7, c10, 4 @ drain WB 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 131 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 133 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 143 mcr p1 [all...]`
H A D	proc-arm946.S	`46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 137 mcr p1 [all...]`
H A D	proc-arm940.S	`39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 52 mcr p15, 0, ip, c7, c10, 4 @ drain WB 56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 112 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 162 2: mcr p1 [all...]`
H A D	proc-arm920.S	`61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 193 1: mcr p1 [all...]`
H A D	proc-sa1100.S	`41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 74 mcr p15, 0, ip, c7, c10, 4 @ drain WB 76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 110 mcr p1 [all...]`
H A D	proc-xsc3.S	`68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 92 mcr p15, 0, r0, c1, c0, 0 @ disable caches 112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 137 mcr p14, 0, r0, c7, c0, 0 @ go to idle 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 224 1: mcr p1 [all...]`
H A D	cache-v6.S	40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 134 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 141 mcr p1 [all...]
H A D	proc-arm922.S	`63 mcr p15, 0, r0, c1, c0, 0 @ disable caches 79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 87 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 195 1: mcr p1 [all...]`
H A D	proc-feroceon.S	`68 mcr p15, 1, r0, c15, c9, 0 @ clean L2 69 mcr p15, 0, r0, c7, c10, 4 @ drain WB 75 mcr p15, 0, r0, c1, c0, 0 @ disable caches 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 112 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 113 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p1 [all...]`
/kernel/linux/linux-6.6/arch/arm/mm/
H A D	proc-fa526.S	`39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 87 mcr p15, 0, r0, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 108 mcr p1 [all...]`
H A D	proc-arm926.S	`53 mcr p15, 0, r0, c1, c0, 0 @ disable caches 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 109 mcr p1 [all...]`
H A D	proc-mohawk.S	`44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 138 mcr p1 [all...]`
H A D	proc-arm1020.S	`69 mcr p15, 0, r0, c1, c0, 0 @ disable caches 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 93 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 145 mcr p1 [all...]`
H A D	proc-arm925.S	`84 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 mcr p15, 0, ip, c7, c10, 4 @ drain WB 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 131 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 133 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 143 mcr p1 [all...]`
H A D	proc-arm946.S	`46 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 63 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 137 mcr p1 [all...]`
H A D	proc-arm940.S	`39 mcr p15, 0, r0, c1, c0, 0 @ disable caches 50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 52 mcr p15, 0, ip, c7, c10, 4 @ drain WB 56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 112 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 162 2: mcr p1 [all...]`
H A D	proc-arm920.S	`61 mcr p15, 0, r0, c1, c0, 0 @ disable caches 77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 193 1: mcr p1 [all...]`
H A D	proc-sa1100.S	`41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 74 mcr p15, 0, ip, c7, c10, 4 @ drain WB 76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 110 mcr p1 [all...]`
H A D	proc-xsc3.S	`68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 92 mcr p15, 0, r0, c1, c0, 0 @ disable caches 112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 137 mcr p14, 0, r0, c7, c0, 0 @ go to idle 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 224 1: mcr p1 [all...]`
H A D	cache-v6.S	42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 143 mcr p1 [all...]
H A D	proc-arm922.S	`63 mcr p15, 0, r0, c1, c0, 0 @ disable caches 79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 87 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 195 1: mcr p1 [all...]`

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