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/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-divider.c21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); clk_frac_div_round_rate() local
83 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); clk_frac_div_set_rate() local
139 struct tegra_clk_frac_div *divider; tegra_clk_register_divider() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/tegra/
H A Dclk-divider.c21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); clk_frac_div_round_rate() local
83 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); clk_frac_div_set_rate() local
139 struct tegra_clk_frac_div *divider; tegra_clk_register_divider() local
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/kernel/linux/linux-5.10/drivers/clk/ti/
H A Ddivider.c40 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
46 if (divider->table) { in _setup_mask()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
53 max_val = divider->max; in _setup_mask()
55 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
56 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
60 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
65 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
68 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
70 if (divider in _get_div()
90 _get_val(struct clk_omap_divider *divider, u8 div) _get_val() argument
104 struct clk_omap_divider *divider = to_clk_omap_divider(hw); ti_clk_divider_recalc_rate() local
138 _is_valid_div(struct clk_omap_divider *divider, unsigned int div) _is_valid_div() argument
179 struct clk_omap_divider *divider = to_clk_omap_divider(hw); ti_clk_divider_bestdiv() local
246 struct clk_omap_divider *divider; ti_clk_divider_set_rate() local
282 struct clk_omap_divider *divider = to_clk_omap_divider(hw); clk_divider_save_context() local
299 struct clk_omap_divider *divider = to_clk_omap_divider(hw); clk_divider_restore_context() local
339 ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, u8 flags, struct clk_omap_divider *divider) ti_clk_parse_divider_data() argument
442 _populate_divider_min_max(struct device_node *node, struct clk_omap_divider *divider) _populate_divider_min_max() argument
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/kernel/linux/linux-6.6/drivers/clk/ti/
H A Ddivider.c32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
45 max_val = divider->max; in _setup_mask()
47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
48 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
52 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
57 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
60 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
62 if (divider in _get_div()
82 _get_val(struct clk_omap_divider *divider, u8 div) _get_val() argument
96 struct clk_omap_divider *divider = to_clk_omap_divider(hw); ti_clk_divider_recalc_rate() local
130 _is_valid_div(struct clk_omap_divider *divider, unsigned int div) _is_valid_div() argument
171 struct clk_omap_divider *divider = to_clk_omap_divider(hw); ti_clk_divider_bestdiv() local
238 struct clk_omap_divider *divider; ti_clk_divider_set_rate() local
274 struct clk_omap_divider *divider = to_clk_omap_divider(hw); clk_divider_save_context() local
291 struct clk_omap_divider *divider = to_clk_omap_divider(hw); clk_divider_restore_context() local
331 ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, u8 flags, struct clk_omap_divider *divider) ti_clk_parse_divider_data() argument
434 _populate_divider_min_max(struct device_node *node, struct clk_omap_divider *divider) _populate_divider_min_max() argument
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/kernel/linux/linux-5.10/drivers/clk/mvebu/
H A Ddove-divider.c3 * Marvell Dove PMU Core PLL divider driver
15 #include "dove-divider.h"
53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider in dove_calc_divider()
102 unsigned int divider = dove_get_divider(dc); dove_recalc_rate() local
116 int divider; dove_round_rate() local
135 int divider; dove_set_clock() local
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/kernel/linux/linux-6.6/drivers/clk/mvebu/
H A Ddove-divider.c3 * Marvell Dove PMU Core PLL divider driver
15 #include "dove-divider.h"
53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider in dove_calc_divider()
102 unsigned int divider = dove_get_divider(dc); dove_recalc_rate() local
116 int divider; dove_round_rate() local
135 int divider; dove_set_clock() local
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/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Dclk-regmap-divider.c11 #include "clk-regmap-divider.h"
21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
45 struct clk_regmap_div *divider in div_set_rate() local
60 struct clk_regmap_div *divider = to_clk_regmap_div(hw); div_recalc_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dclk-regmap-divider.c11 #include "clk-regmap-divider.h"
21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
45 struct clk_regmap_div *divider in div_set_rate() local
60 struct clk_regmap_div *divider = to_clk_regmap_div(hw); div_recalc_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-divider.c7 * Adjustable divider clock implementation
20 * DOC: basic adjustable divider clock that cannot gate
29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
32 return ioread32be(divider->reg); in clk_div_readl()
34 return readl(divider->reg); in clk_div_readl()
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
40 iowrite32be(val, divider->reg); in clk_div_writel()
42 writel(val, divider in clk_div_writel()
152 struct clk_divider *divider = to_clk_divider(hw); clk_divider_recalc_rate() local
431 struct clk_divider *divider = to_clk_divider(hw); clk_divider_round_rate() local
452 struct clk_divider *divider = to_clk_divider(hw); clk_divider_determine_rate() local
490 struct clk_divider *divider = to_clk_divider(hw); clk_divider_set_rate() local
[all...]
H A Dclk-milbeaut.c379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_round_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider in m10v_clk_divider_round_rate()
413 struct m10v_clk_divider *divider = to_m10v_div(hw); m10v_clk_divider_set_rate() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-divider.c7 * Adjustable divider clock implementation
19 * DOC: basic adjustable divider clock that cannot gate
28 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
30 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
31 return ioread32be(divider->reg); in clk_div_readl()
33 return readl(divider->reg); in clk_div_readl()
36 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
38 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
39 iowrite32be(val, divider->reg); in clk_div_writel()
41 writel(val, divider in clk_div_writel()
151 struct clk_divider *divider = to_clk_divider(hw); clk_divider_recalc_rate() local
383 struct clk_divider *divider = to_clk_divider(hw); clk_divider_round_rate() local
421 struct clk_divider *divider = to_clk_divider(hw); clk_divider_set_rate() local
[all...]
H A Dclk-milbeaut.c379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_round_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider in m10v_clk_divider_round_rate()
413 struct m10v_clk_divider *divider = to_m10v_div(hw); m10v_clk_divider_set_rate() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/rockchip/
H A Dclk-half-divider.c25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
60 * The maximum divider we can use without overflowing in clk_half_divider_bestdiv()
70 * parent rate, so return the divider immediately. in clk_half_divider_bestdiv()
98 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
111 struct clk_divider *divider in clk_half_divider_set_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk-half-divider.c25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
60 * The maximum divider we can use without overflowing in clk_half_divider_bestdiv()
70 * parent rate, so return the divider immediately. in clk_half_divider_bestdiv()
98 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
111 struct clk_divider *divider in clk_half_divider_set_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/xilinx/
H A Dclk-xlnx-clock-wizard.c74 /* Extract divider instance from clock hardware instance */
110 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
113 * @base: base address of register containing the divider
114 * @offset: offset address of register containing the divider
115 * @shift: shift to the divider bit field
116 * @width: width of the divider bit field
117 * @flags: clk_wzrd divider flags
118 * @table: array of value/divider pairs, last entry should have div = 0
120 * @d: value of the common divider
121 * @o: value of the leaf divider
153 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_recalc_rate() local
170 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_dynamic_reconfig() local
229 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_get_divisors() local
257 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_dynamic_all_nolock() local
305 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_dynamic_all() local
321 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_recalc_rate_all() local
339 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_round_rate_all() local
380 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_recalc_ratef() local
396 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); clk_wzrd_dynamic_reconfig_f() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-fixup-div.c15 * struct clk_fixup_div - imx integer fixup divider clock
16 * @divider: the parent class
20 * The imx fixup divider clock is a subclass of basic clk_divider
24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
57 unsigned int divider, valu in clk_fixup_div_set_rate() local
[all...]
H A Dclk-composite-8m.c31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
95 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
107 spin_lock_irqsave(divider in imx8m_clk_composite_divider_set_rate()
[all...]
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-fixup-div.c15 * struct clk_fixup_div - imx integer fixup divider clock
16 * @divider: the parent class
20 * The imx fixup divider clock is a subclass of basic clk_divider
24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
57 unsigned int divider, valu in clk_fixup_div_set_rate() local
[all...]
H A Dclk-composite-8m.c31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
95 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
107 spin_lock_irqsave(divider in imx8m_clk_composite_divider_set_rate()
127 struct clk_divider *divider = to_clk_divider(hw); imx8m_divider_determine_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/stm32/
H A Dclk-stm32-core.c210 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_get_rate() local
214 val = readl(base + divider->offset) >> divider->shift; in stm32_divider_get_rate()
215 val &= clk_div_mask(divider->width); in stm32_divider_get_rate()
216 div = _get_div(divider->table, val, divider->flags, divider->width); in stm32_divider_get_rate()
219 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in stm32_divider_get_rate()
233 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_set_rate() local
237 value = divider_get_val(rate, parent_rate, divider in stm32_divider_set_rate()
356 const struct stm32_div_cfg *divider; clk_stm32_divider_round_rate() local
433 const struct stm32_div_cfg *divider; clk_stm32_composite_determine_rate() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/mxs/
H A Dclk-div.c12 * struct clk_div - mxs integer divider clock
13 * @divider: the parent class
18 * The mxs divider clock is a subclass of basic clk_divider with an
22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider in clk_div_set_rate()
[all...]
/kernel/linux/linux-6.6/drivers/clk/mxs/
H A Dclk-div.c12 * struct clk_div - mxs integer divider clock
13 * @divider: the parent class
18 * The mxs divider clock is a subclass of basic clk_divider with an
22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider in clk_div_set_rate()
[all...]
/kernel/linux/linux-5.10/drivers/clk/zynqmp/
H A Ddivider.c7 * Adjustable divider clock implementation
16 * DOC: basic adjustable divider clock that cannot gate
32 * struct zynqmp_clk_divider - adjustable divider clock
35 * @is_frac: The divider is a fractional divider
72 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
81 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
83 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
84 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
91 pr_warn_once("%s() get divider faile in zynqmp_clk_divider_recalc_rate()
124 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); zynqmp_clk_divider_round_rate() local
171 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); zynqmp_clk_divider_set_rate() local
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/kernel/linux/linux-6.6/drivers/clk/zynqmp/
H A Ddivider.c7 * Adjustable divider clock implementation
16 * DOC: basic adjustable divider clock that cannot gate
32 * struct zynqmp_clk_divider - adjustable divider clock
35 * @is_frac: The divider is a fractional divider
73 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
82 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
85 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
92 pr_debug("%s() get divider faile in zynqmp_clk_divider_recalc_rate()
125 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); zynqmp_clk_divider_round_rate() local
172 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); zynqmp_clk_divider_set_rate() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/baikal-t1/
H A Dccu-div.c79 unsigned long divider) in ccu_div_var_update_clkdiv()
86 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
212 unsigned long divider; in ccu_div_var_recalc_rate() local
216 divider = ccu_div_get(div->mask, val); in ccu_div_var_recalc_rate()
218 return ccu_div_calc_freq(parent_rate, divider); in ccu_div_var_recalc_rate()
225 unsigned long divider; in ccu_div_var_calc_divider() local
227 divider = parent_rate / rate; in ccu_div_var_calc_divider()
228 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN, in ccu_div_var_calc_divider()
236 unsigned long divider; in ccu_div_var_round_rate() local
238 divider in ccu_div_var_round_rate()
77 ccu_div_var_update_clkdiv(struct ccu_div *div, unsigned long parent_rate, unsigned long divider) ccu_div_var_update_clkdiv() argument
252 unsigned long flags, divider; ccu_div_var_set_rate_slow() local
286 unsigned long flags, divider; ccu_div_var_set_rate_fast() local
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