Lines Matching refs:divider
79 unsigned long divider)
86 nd = ccu_div_lock_delay_ns(parent_rate, divider);
212 unsigned long divider;
216 divider = ccu_div_get(div->mask, val);
218 return ccu_div_calc_freq(parent_rate, divider);
225 unsigned long divider;
227 divider = parent_rate / rate;
228 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
236 unsigned long divider;
238 divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask);
240 return ccu_div_calc_freq(*parent_rate, divider);
244 * This method is used for the clock divider blocks, which support the
252 unsigned long flags, divider;
256 divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
257 if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) {
258 divider = 0;
260 if (divider == 1 || divider == 2)
261 divider = 0;
262 else if (divider == 3)
263 divider = 4;
266 val = ccu_div_prep(div->mask, divider);
270 ret = ccu_div_var_update_clkdiv(div, parent_rate, divider);
279 * This method is used for the clock divider blocks, which don't support
286 unsigned long flags, divider;
289 divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
290 val = ccu_div_prep(div->mask, divider);
293 * Also disable the clock divider block if it was enabled by default
309 return ccu_div_calc_freq(parent_rate, div->divider);
317 return ccu_div_calc_freq(*parent_rate, div->divider);
447 *val = div->divider;
630 div->divider = div_init->divider;
635 div->divider = div_init->divider;