Lines Matching refs:divider
74 /* Extract divider instance from clock hardware instance */
110 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
113 * @base: base address of register containing the divider
114 * @offset: offset address of register containing the divider
115 * @shift: shift to the divider bit field
116 * @width: width of the divider bit field
117 * @flags: clk_wzrd divider flags
118 * @table: array of value/divider pairs, last entry should have div = 0
120 * @d: value of the common divider
121 * @o: value of the leaf divider
135 spinlock_t *lock; /* divider lock */
153 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
154 void __iomem *div_addr = divider->base + divider->offset;
157 val = readl(div_addr) >> divider->shift;
158 val &= div_mask(divider->width);
160 return divider_recalc_rate(hw, parent_rate, val, divider->table,
161 divider->flags, divider->width);
170 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
171 void __iomem *div_addr = divider->base + divider->offset;
173 if (divider->lock)
174 spin_lock_irqsave(divider->lock, flags);
176 __acquire(divider->lock);
188 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
196 divider->base + WZRD_DR_INIT_REG_OFFSET);
198 divider->base + WZRD_DR_INIT_REG_OFFSET);
201 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET,
205 if (divider->lock)
206 spin_unlock_irqrestore(divider->lock, flags);
208 __release(divider->lock);
229 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
242 divider->m = m;
243 divider->d = d;
244 divider->o = o;
257 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
266 vco_freq = DIV_ROUND_CLOSEST(parent_rate * divider->m, divider->d);
278 writel(reg, divider->base + WZRD_CLK_CFG_REG(2));
280 reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |
281 FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);
282 writel(reg, divider->base + WZRD_CLK_CFG_REG(0));
283 writel(divider->o, divider->base + WZRD_CLK_CFG_REG(2));
284 writel(0, divider->base + WZRD_CLK_CFG_REG(3));
286 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
294 divider->base + WZRD_DR_INIT_REG_OFFSET);
297 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
305 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
309 spin_lock_irqsave(divider->lock, flags);
313 spin_unlock_irqrestore(divider->lock, flags);
321 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
324 reg = readl(divider->base + WZRD_CLK_CFG_REG(0));
327 reg = readl(divider->base + WZRD_CLK_CFG_REG(2));
332 return divider_recalc_rate(hw, parent_rate * m, div, divider->table,
333 divider->flags, divider->width);
339 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
348 m = divider->m;
349 d = divider->d;
350 o = divider->o;
353 int_freq = divider_recalc_rate(hw, *prate * m, div, divider->table,
354 divider->flags, divider->width);
380 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
381 void __iomem *div_addr = divider->base + divider->offset;
384 div = val & div_mask(divider->width);
396 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
397 void __iomem *div_addr = divider->base + divider->offset;
414 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
422 divider->base + WZRD_DR_INIT_REG_OFFSET);
424 divider->base + WZRD_DR_INIT_REG_OFFSET);
427 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
705 dev_err(&pdev->dev, "unable to register divider clock\n");
743 "unable to register divider clock\n");