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Searched refs:control_reg (Results 1 - 25 of 62) sorted by relevance

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/kernel/linux/linux-5.10/sound/pci/echoaudio/
H A Dechoaudio_3g.c145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) in set_spdif_bits() argument
147 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; in set_spdif_bits()
151 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits()
155 control_reg |= E3G_SPDIF_SAMPLE_RATE0; in set_spdif_bits()
158 control_reg |= E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits()
163 control_reg |= E3G_SPDIF_PRO_MODE; in set_spdif_bits()
166 control_reg |= E3G_SPDIF_NOT_AUDIO; in set_spdif_bits()
168 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | in set_spdif_bits()
171 return control_reg; in set_spdif_bits()
179 u32 control_reg; in set_professional_spdif() local
260 u32 control_reg, clock, base_rate, frq_reg; set_sample_rate() local
331 u32 control_reg, clocks_from_dsp; set_input_clock() local
379 u32 control_reg; dsp_set_digital_mode() local
[all...]
H A Dgina24_dsp.c124 u32 control_reg; in load_asic() local
154 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
155 err = write_control_reg(chip, control_reg, true); in load_asic()
164 u32 control_reg, clock; in set_sample_rate() local
182 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
183 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
198 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
223 control_reg |= clock; in set_sample_rate()
229 return write_control_reg(chip, control_reg, false); in set_sample_rate()
236 u32 control_reg, clocks_from_ds in set_input_clock() local
284 u32 control_reg; dsp_set_digital_mode() local
[all...]
H A Dmona_dsp.c117 u32 control_reg; in load_asic() local
150 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
151 err = write_control_reg(chip, control_reg, true); in load_asic()
198 u32 control_reg, clock; in set_sample_rate() local
244 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
245 control_reg &= GML_CLOCK_CLEAR_MASK; in set_sample_rate()
246 control_reg &= GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
261 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
286 control_reg |= clock; in set_sample_rate()
293 return write_control_reg(chip, control_reg, force_writ in set_sample_rate()
300 u32 control_reg, clocks_from_dsp; set_input_clock() local
361 u32 control_reg; dsp_set_digital_mode() local
[all...]
H A Dlayla24_dsp.c159 u32 control_reg, clock, base_rate; in set_sample_rate() local
176 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
177 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
194 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
219 control_reg |= GML_DOUBLE_SPEED_MODE; in set_sample_rate()
237 control_reg |= clock; in set_sample_rate()
242 "set_sample_rate: %d clock %d\n", rate, control_reg); in set_sample_rate()
244 return write_control_reg(chip, control_reg, false); in set_sample_rate()
251 u32 control_reg, clocks_from_dsp; in set_input_clock() local
254 control_reg in set_input_clock()
332 u32 control_reg; dsp_set_digital_mode() local
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H A Dechoaudio_gml.c158 u32 control_reg; in set_professional_spdif() local
162 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_professional_spdif()
163 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK; in set_professional_spdif()
166 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT | in set_professional_spdif()
170 control_reg |= GML_SPDIF_PRO_MODE; in set_professional_spdif()
174 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
178 control_reg |= GML_SPDIF_SAMPLE_RATE0; in set_professional_spdif()
181 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif()
188 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
192 control_reg | in set_professional_spdif()
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H A Dindigodj_dsp.c92 u32 control_reg; in set_sample_rate() local
96 control_reg = MIA_96000; in set_sample_rate()
99 control_reg = MIA_88200; in set_sample_rate()
102 control_reg = MIA_48000; in set_sample_rate()
105 control_reg = MIA_44100; in set_sample_rate()
108 control_reg = MIA_32000; in set_sample_rate()
117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
122 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
H A Dindigo_dsp.c92 u32 control_reg; in set_sample_rate() local
96 control_reg = MIA_96000; in set_sample_rate()
99 control_reg = MIA_88200; in set_sample_rate()
102 control_reg = MIA_48000; in set_sample_rate()
105 control_reg = MIA_44100; in set_sample_rate()
108 control_reg = MIA_32000; in set_sample_rate()
117 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
122 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
H A Dmia_dsp.c109 u32 control_reg; in set_sample_rate() local
113 control_reg = MIA_96000; in set_sample_rate()
116 control_reg = MIA_88200; in set_sample_rate()
119 control_reg = MIA_48000; in set_sample_rate()
122 control_reg = MIA_44100; in set_sample_rate()
125 control_reg = MIA_32000; in set_sample_rate()
135 control_reg |= MIA_SPDIF; in set_sample_rate()
138 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
143 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
H A Dindigo_express_dsp.c31 u32 clock, control_reg, old_control_reg; in set_sample_rate() local
37 control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK; in set_sample_rate()
62 control_reg |= clock; in set_sample_rate()
63 if (control_reg != old_control_reg) { in set_sample_rate()
66 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
/kernel/linux/linux-6.6/sound/pci/echoaudio/
H A Dechoaudio_3g.c145 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) in set_spdif_bits() argument
147 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; in set_spdif_bits()
151 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits()
155 control_reg |= E3G_SPDIF_SAMPLE_RATE0; in set_spdif_bits()
158 control_reg |= E3G_SPDIF_SAMPLE_RATE1; in set_spdif_bits()
163 control_reg |= E3G_SPDIF_PRO_MODE; in set_spdif_bits()
166 control_reg |= E3G_SPDIF_NOT_AUDIO; in set_spdif_bits()
168 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | in set_spdif_bits()
171 return control_reg; in set_spdif_bits()
179 u32 control_reg; in set_professional_spdif() local
260 u32 control_reg, clock, base_rate, frq_reg; set_sample_rate() local
331 u32 control_reg, clocks_from_dsp; set_input_clock() local
379 u32 control_reg; dsp_set_digital_mode() local
[all...]
H A Dgina24_dsp.c126 u32 control_reg; in load_asic() local
156 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
157 err = write_control_reg(chip, control_reg, true); in load_asic()
166 u32 control_reg, clock; in set_sample_rate() local
184 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
185 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
200 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
225 control_reg |= clock; in set_sample_rate()
231 return write_control_reg(chip, control_reg, false); in set_sample_rate()
238 u32 control_reg, clocks_from_ds in set_input_clock() local
286 u32 control_reg; dsp_set_digital_mode() local
[all...]
H A Dmona_dsp.c119 u32 control_reg; in load_asic() local
152 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
153 err = write_control_reg(chip, control_reg, true); in load_asic()
200 u32 control_reg, clock; in set_sample_rate() local
246 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
247 control_reg &= GML_CLOCK_CLEAR_MASK; in set_sample_rate()
248 control_reg &= GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
263 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
288 control_reg |= clock; in set_sample_rate()
295 return write_control_reg(chip, control_reg, force_writ in set_sample_rate()
302 u32 control_reg, clocks_from_dsp; set_input_clock() local
363 u32 control_reg; dsp_set_digital_mode() local
[all...]
H A Dlayla24_dsp.c162 u32 control_reg, clock, base_rate; in set_sample_rate() local
179 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_sample_rate()
180 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK; in set_sample_rate()
197 if (control_reg & GML_SPDIF_PRO_MODE) in set_sample_rate()
222 control_reg |= GML_DOUBLE_SPEED_MODE; in set_sample_rate()
240 control_reg |= clock; in set_sample_rate()
245 "set_sample_rate: %d clock %d\n", rate, control_reg); in set_sample_rate()
247 return write_control_reg(chip, control_reg, false); in set_sample_rate()
254 u32 control_reg, clocks_from_dsp; in set_input_clock() local
257 control_reg in set_input_clock()
335 u32 control_reg; dsp_set_digital_mode() local
[all...]
H A Dechoaudio_gml.c158 u32 control_reg; in set_professional_spdif() local
162 control_reg = le32_to_cpu(chip->comm_page->control_register); in set_professional_spdif()
163 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK; in set_professional_spdif()
166 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT | in set_professional_spdif()
170 control_reg |= GML_SPDIF_PRO_MODE; in set_professional_spdif()
174 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
178 control_reg |= GML_SPDIF_SAMPLE_RATE0; in set_professional_spdif()
181 control_reg |= GML_SPDIF_SAMPLE_RATE1; in set_professional_spdif()
188 control_reg |= GML_SPDIF_SAMPLE_RATE0 | in set_professional_spdif()
192 control_reg | in set_professional_spdif()
[all...]
H A Dindigo_dsp.c94 u32 control_reg; in set_sample_rate() local
98 control_reg = MIA_96000; in set_sample_rate()
101 control_reg = MIA_88200; in set_sample_rate()
104 control_reg = MIA_48000; in set_sample_rate()
107 control_reg = MIA_44100; in set_sample_rate()
110 control_reg = MIA_32000; in set_sample_rate()
119 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
124 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
H A Dindigodj_dsp.c94 u32 control_reg; in set_sample_rate() local
98 control_reg = MIA_96000; in set_sample_rate()
101 control_reg = MIA_88200; in set_sample_rate()
104 control_reg = MIA_48000; in set_sample_rate()
107 control_reg = MIA_44100; in set_sample_rate()
110 control_reg = MIA_32000; in set_sample_rate()
119 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
124 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
H A Dmia_dsp.c111 u32 control_reg; in set_sample_rate() local
115 control_reg = MIA_96000; in set_sample_rate()
118 control_reg = MIA_88200; in set_sample_rate()
121 control_reg = MIA_48000; in set_sample_rate()
124 control_reg = MIA_44100; in set_sample_rate()
127 control_reg = MIA_32000; in set_sample_rate()
137 control_reg |= MIA_SPDIF; in set_sample_rate()
140 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) { in set_sample_rate()
145 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
H A Dindigo_express_dsp.c31 u32 clock, control_reg, old_control_reg; in set_sample_rate() local
37 control_reg = old_control_reg & ~INDIGO_EXPRESS_CLOCK_MASK; in set_sample_rate()
62 control_reg |= clock; in set_sample_rate()
63 if (control_reg != old_control_reg) { in set_sample_rate()
66 chip->comm_page->control_register = cpu_to_le32(control_reg); in set_sample_rate()
/kernel/linux/linux-5.10/drivers/scsi/pcmcia/
H A Dnsp_message.c15 unsigned char data_reg, control_reg; in nsp_message_in() local
33 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in()
34 control_reg |= SCSI_ACK; in nsp_message_in()
35 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
41 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in()
42 control_reg &= ~SCSI_ACK; in nsp_message_in()
43 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
/kernel/linux/linux-6.6/drivers/scsi/pcmcia/
H A Dnsp_message.c15 unsigned char data_reg, control_reg; in nsp_message_in() local
33 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in()
34 control_reg |= SCSI_ACK; in nsp_message_in()
35 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
41 control_reg = nsp_index_read(base, SCSIBUSCTRL); in nsp_message_in()
42 control_reg &= ~SCSI_ACK; in nsp_message_in()
43 nsp_index_write(base, SCSIBUSCTRL, control_reg); in nsp_message_in()
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-palmas.c35 unsigned int control_reg; member
67 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
72 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
92 cinfo->clk_desc->control_reg, in palmas_clks_unprepare()
96 cinfo->clk_desc->control_reg, ret); in palmas_clks_unprepare()
109 cinfo->clk_desc->control_reg, &val); in palmas_clks_is_prepared()
112 cinfo->clk_desc->control_reg, ret); in palmas_clks_is_prepared()
138 .control_reg = PALMAS_CLK32KG_CTRL,
154 .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
211 cinfo->clk_desc->control_reg, in palmas_clks_init_configure()
[all...]
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-palmas.c26 unsigned int control_reg; member
58 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
63 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
83 cinfo->clk_desc->control_reg, in palmas_clks_unprepare()
87 cinfo->clk_desc->control_reg, ret); in palmas_clks_unprepare()
100 cinfo->clk_desc->control_reg, &val); in palmas_clks_is_prepared()
103 cinfo->clk_desc->control_reg, ret); in palmas_clks_is_prepared()
129 .control_reg = PALMAS_CLK32KG_CTRL,
145 .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
202 cinfo->clk_desc->control_reg, in palmas_clks_init_configure()
[all...]
/kernel/linux/linux-5.10/drivers/watchdog/
H A Dts72xx_wdt.c31 /* priv->control_reg */
45 void __iomem *control_reg; member
56 writeb(priv->regval, priv->control_reg); in ts72xx_wdt_start()
66 writeb(TS72XX_WDT_CTRL_DISABLE, priv->control_reg); in ts72xx_wdt_stop()
134 priv->control_reg = devm_platform_ioremap_resource(pdev, 0); in ts72xx_wdt_probe()
135 if (IS_ERR(priv->control_reg)) in ts72xx_wdt_probe()
136 return PTR_ERR(priv->control_reg); in ts72xx_wdt_probe()
/kernel/linux/linux-6.6/drivers/watchdog/
H A Dts72xx_wdt.c29 /* priv->control_reg */
43 void __iomem *control_reg; member
54 writeb(priv->regval, priv->control_reg); in ts72xx_wdt_start()
64 writeb(TS72XX_WDT_CTRL_DISABLE, priv->control_reg); in ts72xx_wdt_stop()
132 priv->control_reg = devm_platform_ioremap_resource(pdev, 0); in ts72xx_wdt_probe()
133 if (IS_ERR(priv->control_reg)) in ts72xx_wdt_probe()
134 return PTR_ERR(priv->control_reg); in ts72xx_wdt_probe()
/kernel/linux/linux-5.10/drivers/clk/ti/
H A Dapll.c63 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_enable()
66 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_enable()
102 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_disable()
105 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_disable()
116 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_is_enabled()
220 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); in of_dra7_apll_setup()
249 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_is_enabled()
275 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_enable()
278 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in omap2_apll_enable()
305 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_disable()
[all...]

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