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/kernel/linux/linux-5.10/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dpearl_pcie_regs.h8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00)
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04)
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10)
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14)
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base)
[all...]
H A Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base)
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dpearl_pcie_regs.h8 #define PCIE_HDP_CTRL(base) ((base) + 0x2c00)
9 #define PCIE_HDP_AXI_CTRL(base) ((base) + 0x2c04)
10 #define PCIE_HDP_HOST_WR_DESC0(base) ((base) + 0x2c10)
11 #define PCIE_HDP_HOST_WR_DESC0_H(base) ((base) + 0x2c14)
12 #define PCIE_HDP_HOST_WR_DESC1(base) ((base)
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H A Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base)
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28)
12 #define RING_TAIL(base) _MMIO((base) + 0x30)
14 #define RING_HEAD(base) _MMIO((base) + 0x34)
18 #define RING_START(base) _MMIO((base) + 0x38)
19 #define RING_CTL(base) _MMIO((base)
[all...]
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-imx6ul.c117 void __iomem *base; in imx6ul_clocks_init() local
137 base = of_iomap(np, 0); in imx6ul_clocks_init()
139 WARN_ON(!base); in imx6ul_clocks_init()
141 hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
142 hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
143 hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
144 hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
145 hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
146 hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
147 hws[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base in imx6ul_clocks_init()
[all...]
H A Dclk-imx6sll.c82 void __iomem *base; in imx6sll_clocks_init() local
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
107 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
108 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
109 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
110 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
111 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); in imx6sll_clocks_init()
112 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); in imx6sll_clocks_init()
113 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base in imx6sll_clocks_init()
[all...]
H A Dclk-imx8mm.c298 void __iomem *base; in imx8mm_clocks_probe() local
318 base = of_iomap(np, 0); in imx8mm_clocks_probe()
320 if (WARN_ON(!base)) in imx8mm_clocks_probe()
323 hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
324 hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
325 hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
326 hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
327 hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
328 hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
329 hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base in imx8mm_clocks_probe()
[all...]
H A Dclk-imx7d.c383 void __iomem *base; in imx7d_clocks_init() local
398 base = of_iomap(np, 0); in imx7d_clocks_init()
399 WARN_ON(!base); in imx7d_clocks_init()
402 hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
403 hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
404 hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
405 hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
406 hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
407 hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
409 hws[IMX7D_PLL_ARM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base in imx7d_clocks_init()
[all...]
H A Dclk-imx8mq.c280 void __iomem *base; in imx8mq_clocks_probe() local
300 base = devm_of_iomap(dev, np, 0, NULL); in imx8mq_clocks_probe()
302 if (WARN_ON(IS_ERR(base))) { in imx8mq_clocks_probe()
303 err = PTR_ERR(base); in imx8mq_clocks_probe()
307 hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
308 hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
309 hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
310 hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
311 hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
312 hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base in imx8mq_clocks_probe()
[all...]
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imx6sll.c82 void __iomem *base; in imx6sll_clocks_init() local
102 base = of_iomap(np, 0); in imx6sll_clocks_init()
104 WARN_ON(!base); in imx6sll_clocks_init()
107 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x0)); in imx6sll_clocks_init()
108 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x10)); in imx6sll_clocks_init()
109 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x20)); in imx6sll_clocks_init()
110 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x30)); in imx6sll_clocks_init()
111 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0x70)); in imx6sll_clocks_init()
112 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base + xPLL_CLR(0xa0)); in imx6sll_clocks_init()
113 writel_relaxed(CCM_ANALOG_PLL_BYPASS, base in imx6sll_clocks_init()
[all...]
H A Dclk-imx8mq.c288 void __iomem *base; in imx8mq_clocks_probe() local
308 base = devm_of_iomap(dev, np, 0, NULL); in imx8mq_clocks_probe()
310 if (WARN_ON(IS_ERR(base))) { in imx8mq_clocks_probe()
311 err = PTR_ERR(base); in imx8mq_clocks_probe()
315 hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
316 hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
317 hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
318 hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
319 hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mq_clocks_probe()
320 hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base in imx8mq_clocks_probe()
[all...]
H A Dclk-imx7d.c383 void __iomem *base; in imx7d_clocks_init() local
398 base = of_iomap(np, 0); in imx7d_clocks_init()
399 WARN_ON(!base); in imx7d_clocks_init()
402 hws[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_hw_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
403 hws[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_hw_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
404 hws[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_hw_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
405 hws[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_hw_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
406 hws[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_hw_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
407 hws[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_hw_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel)); in imx7d_clocks_init()
409 hws[IMX7D_PLL_ARM_MAIN] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base in imx7d_clocks_init()
[all...]
H A Dclk-imx8mm.c303 void __iomem *base; in imx8mm_clocks_probe() local
323 base = of_iomap(np, 0); in imx8mm_clocks_probe()
325 if (WARN_ON(!base)) in imx8mm_clocks_probe()
328 hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
329 hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
330 hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
331 hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
332 hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
333 hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mm_clocks_probe()
334 hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base in imx8mm_clocks_probe()
[all...]
/kernel/linux/linux-5.10/drivers/scsi/
H A Dnsp32_io.h12 static inline void nsp32_write1(unsigned int base, in nsp32_write1() argument
16 outb(val, (base + index)); in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1() argument
22 return inb(base + index); in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2() argument
29 outw(val, (base + index)); in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2() argument
35 return inw(base + index); in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4() argument
42 outl(val, (base in nsp32_write4()
45 nsp32_read4(unsigned int base, unsigned int index) nsp32_read4() argument
53 nsp32_mmio_write1(unsigned long base, unsigned int index, unsigned char val) nsp32_mmio_write1() argument
64 nsp32_mmio_read1(unsigned long base, unsigned int index) nsp32_mmio_read1() argument
74 nsp32_mmio_write2(unsigned long base, unsigned int index, unsigned short val) nsp32_mmio_write2() argument
85 nsp32_mmio_read2(unsigned long base, unsigned int index) nsp32_mmio_read2() argument
95 nsp32_mmio_write4(unsigned long base, unsigned int index, unsigned long val) nsp32_mmio_write4() argument
106 nsp32_mmio_read4(unsigned long base, unsigned int index) nsp32_mmio_read4() argument
118 nsp32_index_read1(unsigned int base, unsigned int reg) nsp32_index_read1() argument
125 nsp32_index_write1(unsigned int base, unsigned int reg, unsigned char val) nsp32_index_write1() argument
133 nsp32_index_read2(unsigned int base, unsigned int reg) nsp32_index_read2() argument
140 nsp32_index_write2(unsigned int base, unsigned int reg, unsigned short val) nsp32_index_write2() argument
148 nsp32_index_read4(unsigned int base, unsigned int reg) nsp32_index_read4() argument
160 nsp32_index_write4(unsigned int base, unsigned int reg, unsigned long val) nsp32_index_write4() argument
176 nsp32_mmio_index_read1(unsigned long base, unsigned int reg) nsp32_mmio_index_read1() argument
188 nsp32_mmio_index_write1(unsigned long base, unsigned int reg, unsigned char val) nsp32_mmio_index_write1() argument
201 nsp32_mmio_index_read2(unsigned long base, unsigned int reg) nsp32_mmio_index_read2() argument
213 nsp32_mmio_index_write2(unsigned long base, unsigned int reg, unsigned short val) nsp32_mmio_index_write2() argument
228 nsp32_multi_read4(unsigned int base, unsigned int reg, void *buf, unsigned long count) nsp32_multi_read4() argument
236 nsp32_fifo_read(unsigned int base, void *buf, unsigned long count) nsp32_fifo_read() argument
243 nsp32_multi_write4(unsigned int base, unsigned int reg, void *buf, unsigned long count) nsp32_multi_write4() argument
251 nsp32_fifo_write(unsigned int base, void *buf, unsigned long count) nsp32_fifo_write() argument
[all...]
/kernel/linux/linux-6.6/drivers/scsi/
H A Dnsp32_io.h12 static inline void nsp32_write1(unsigned int base, in nsp32_write1() argument
16 outb(val, (base + index)); in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1() argument
22 return inb(base + index); in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2() argument
29 outw(val, (base + index)); in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2() argument
35 return inw(base + index); in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4() argument
42 outl(val, (base in nsp32_write4()
45 nsp32_read4(unsigned int base, unsigned int index) nsp32_read4() argument
53 nsp32_mmio_write1(unsigned long base, unsigned int index, unsigned char val) nsp32_mmio_write1() argument
64 nsp32_mmio_read1(unsigned long base, unsigned int index) nsp32_mmio_read1() argument
74 nsp32_mmio_write2(unsigned long base, unsigned int index, unsigned short val) nsp32_mmio_write2() argument
85 nsp32_mmio_read2(unsigned long base, unsigned int index) nsp32_mmio_read2() argument
95 nsp32_mmio_write4(unsigned long base, unsigned int index, unsigned long val) nsp32_mmio_write4() argument
106 nsp32_mmio_read4(unsigned long base, unsigned int index) nsp32_mmio_read4() argument
118 nsp32_index_read1(unsigned int base, unsigned int reg) nsp32_index_read1() argument
125 nsp32_index_write1(unsigned int base, unsigned int reg, unsigned char val) nsp32_index_write1() argument
133 nsp32_index_read2(unsigned int base, unsigned int reg) nsp32_index_read2() argument
140 nsp32_index_write2(unsigned int base, unsigned int reg, unsigned short val) nsp32_index_write2() argument
148 nsp32_index_read4(unsigned int base, unsigned int reg) nsp32_index_read4() argument
160 nsp32_index_write4(unsigned int base, unsigned int reg, unsigned long val) nsp32_index_write4() argument
176 nsp32_mmio_index_read1(unsigned long base, unsigned int reg) nsp32_mmio_index_read1() argument
188 nsp32_mmio_index_write1(unsigned long base, unsigned int reg, unsigned char val) nsp32_mmio_index_write1() argument
201 nsp32_mmio_index_read2(unsigned long base, unsigned int reg) nsp32_mmio_index_read2() argument
213 nsp32_mmio_index_write2(unsigned long base, unsigned int reg, unsigned short val) nsp32_mmio_index_write2() argument
228 nsp32_multi_read4(unsigned int base, unsigned int reg, void *buf, unsigned long count) nsp32_multi_read4() argument
236 nsp32_fifo_read(unsigned int base, void *buf, unsigned long count) nsp32_fifo_read() argument
243 nsp32_multi_write4(unsigned int base, unsigned int reg, void *buf, unsigned long count) nsp32_multi_write4() argument
251 nsp32_fifo_write(unsigned int base, void *buf, unsigned long count) nsp32_fifo_write() argument
[all...]
/kernel/linux/linux-6.6/arch/loongarch/kernel/
H A Dfpu.S28 .macro sc_save_fp base
29 EX fst.d $f0, \base, (0 * FPU_REG_WIDTH)
30 EX fst.d $f1, \base, (1 * FPU_REG_WIDTH)
31 EX fst.d $f2, \base, (2 * FPU_REG_WIDTH)
32 EX fst.d $f3, \base, (3 * FPU_REG_WIDTH)
33 EX fst.d $f4, \base, (4 * FPU_REG_WIDTH)
34 EX fst.d $f5, \base, (5 * FPU_REG_WIDTH)
35 EX fst.d $f6, \base, (6 * FPU_REG_WIDTH)
36 EX fst.d $f7, \base, (7 * FPU_REG_WIDTH)
37 EX fst.d $f8, \base, (
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5_core.c28 void __iomem *base = core->base; in hdmi5_core_ddc_init() local
43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi5_core_ddc_init()
44 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi5_core_ddc_init()
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi5_core_ddc_init()
53 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi5_core_ddc_init()
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi5_core_ddc_init()
60 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi5_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi5_core_ddc_init()
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADD in hdmi5_core_ddc_init()
107 void __iomem *base = core->base; hdmi5_core_ddc_uninit() local
118 void __iomem *base = core->base; hdmi5_core_ddc_read() local
275 void __iomem *base = core->base; hdmi_core_video_config() local
337 void __iomem *base = core->base; hdmi_core_config_video_packetizer() local
367 void __iomem *base = core->base; hdmi_core_write_avi_infoframe() local
423 void __iomem *base = core->base; hdmi_core_write_csc() local
485 void __iomem *base = core->base; hdmi_core_enable_video_path() local
501 void __iomem *base = core->base; hdmi_core_mask_interrupts() local
550 void __iomem *base = core->base; hdmi5_core_handle_irqs() local
622 void __iomem *base = core->base; hdmi5_core_audio_config() local
758 void __iomem *base = core->base; hdmi5_core_audio_infoframe_cfg() local
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5_core.c28 void __iomem *base = core->base; in hdmi5_core_ddc_init() local
43 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi5_core_ddc_init()
44 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi5_core_ddc_init()
49 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi5_core_ddc_init()
53 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi5_core_ddc_init()
55 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi5_core_ddc_init()
60 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi5_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi5_core_ddc_init()
67 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADD in hdmi5_core_ddc_init()
107 void __iomem *base = core->base; hdmi5_core_ddc_uninit() local
118 void __iomem *base = core->base; hdmi5_core_ddc_read() local
275 void __iomem *base = core->base; hdmi_core_video_config() local
337 void __iomem *base = core->base; hdmi_core_config_video_packetizer() local
367 void __iomem *base = core->base; hdmi_core_write_avi_infoframe() local
423 void __iomem *base = core->base; hdmi_core_write_csc() local
485 void __iomem *base = core->base; hdmi_core_enable_video_path() local
501 void __iomem *base = core->base; hdmi_core_mask_interrupts() local
550 void __iomem *base = core->base; hdmi5_core_handle_irqs() local
622 void __iomem *base = core->base; hdmi5_core_audio_config() local
758 void __iomem *base = core->base; hdmi5_core_audio_infoframe_cfg() local
[all...]
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5_core.c41 void __iomem *base = core->base; in hdmi_core_ddc_init() local
56 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
57 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
68 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
75 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
80 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADD in hdmi_core_ddc_init()
120 void __iomem *base = core->base; hdmi_core_ddc_uninit() local
130 void __iomem *base = core->base; hdmi_core_ddc_edid() local
309 void __iomem *base = core->base; hdmi_core_video_config() local
373 void __iomem *base = core->base; hdmi_core_config_video_packetizer() local
411 void __iomem *base = core->base; hdmi_core_write_avi_infoframe() local
467 void __iomem *base = core->base; hdmi_core_csc_config() local
509 void __iomem *base = core->base; hdmi_core_enable_video_path() local
525 void __iomem *base = core->base; hdmi_core_mask_interrupts() local
574 void __iomem *base = core->base; hdmi5_core_handle_irqs() local
637 void __iomem *base = core->base; hdmi5_core_audio_config() local
773 void __iomem *base = core->base; hdmi5_core_audio_infoframe_cfg() local
[all...]
/kernel/linux/linux-6.6/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5_core.c41 void __iomem *base = core->base; in hdmi_core_ddc_init() local
56 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init()
57 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi_core_ddc_init()
62 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init()
66 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init()
68 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init()
73 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init()
75 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init()
80 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADD in hdmi_core_ddc_init()
120 void __iomem *base = core->base; hdmi_core_ddc_uninit() local
130 void __iomem *base = core->base; hdmi_core_ddc_edid() local
307 void __iomem *base = core->base; hdmi_core_video_config() local
371 void __iomem *base = core->base; hdmi_core_config_video_packetizer() local
409 void __iomem *base = core->base; hdmi_core_write_avi_infoframe() local
465 void __iomem *base = core->base; hdmi_core_csc_config() local
507 void __iomem *base = core->base; hdmi_core_enable_video_path() local
523 void __iomem *base = core->base; hdmi_core_mask_interrupts() local
572 void __iomem *base = core->base; hdmi5_core_handle_irqs() local
635 void __iomem *base = core->base; hdmi5_core_audio_config() local
771 void __iomem *base = core->base; hdmi5_core_audio_infoframe_cfg() local
[all...]
/kernel/linux/linux-6.6/tools/testing/memblock/tests/
H A Dbasic_api.c36 * A simple test that adds a memory block of a specified base address
48 .base = SZ_1G, in memblock_add_simple_check()
55 memblock_add(r.base, r.size); in memblock_add_simple_check()
57 ASSERT_EQ(rgn->base, r.base); in memblock_add_simple_check()
69 * A simple test that adds a memory block of a specified base address, size,
81 .base = SZ_1M, in memblock_add_node_simple_check()
88 memblock_add_node(r.base, r.size, 1, MEMBLOCK_HOTPLUG); in memblock_add_node_simple_check()
90 ASSERT_EQ(rgn->base, r.base); in memblock_add_node_simple_check()
441 phys_addr_t base, size = SZ_64; memblock_add_many_check() local
[all...]
/kernel/linux/linux-5.10/drivers/media/platform/s5p-jpeg/
H A Djpeg-hw-exynos4.c16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset() argument
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
22 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode() argument
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
41 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
45 base in exynos4_jpeg_set_enc_dec_mode()
52 __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, unsigned int version) __exynos4_jpeg_set_img_fmt() argument
136 __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, unsigned int version) __exynos4_jpeg_set_enc_out_fmt() argument
169 exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) exynos4_jpeg_set_interrupt() argument
183 exynos4_jpeg_get_int_status(void __iomem *base) exynos4_jpeg_get_int_status() argument
188 exynos4_jpeg_get_fifo_status(void __iomem *base) exynos4_jpeg_get_fifo_status() argument
193 exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) exynos4_jpeg_set_huf_table_enable() argument
207 exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) exynos4_jpeg_set_sys_int_enable() argument
219 exynos4_jpeg_set_stream_buf_address(void __iomem *base, unsigned int address) exynos4_jpeg_set_stream_buf_address() argument
225 exynos4_jpeg_set_stream_size(void __iomem *base, unsigned int x_value, unsigned int y_value) exynos4_jpeg_set_stream_size() argument
233 exynos4_jpeg_set_frame_buf_address(void __iomem *base, struct s5p_jpeg_addr *exynos4_jpeg_addr) exynos4_jpeg_set_frame_buf_address() argument
241 exynos4_jpeg_set_encode_tbl_select(void __iomem *base, enum exynos4_jpeg_img_quality_level level) exynos4_jpeg_set_encode_tbl_select() argument
255 exynos4_jpeg_set_dec_components(void __iomem *base, int n) exynos4_jpeg_set_dec_components() argument
265 exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x) exynos4_jpeg_select_dec_q_tbl() argument
275 exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x) exynos4_jpeg_select_dec_h_tbl() argument
285 exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt) exynos4_jpeg_set_encode_hoff_cnt() argument
293 exynos4_jpeg_get_stream_size(void __iomem *base) exynos4_jpeg_get_stream_size() argument
298 exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size) exynos4_jpeg_set_dec_bitstream_size() argument
303 exynos4_jpeg_get_frame_size(void __iomem *base, unsigned int *width, unsigned int *height) exynos4_jpeg_get_frame_size() argument
312 exynos4_jpeg_get_frame_fmt(void __iomem *base) exynos4_jpeg_get_frame_fmt() argument
318 exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size) exynos4_jpeg_set_timer_count() argument
[all...]
/kernel/linux/linux-6.6/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-hw-exynos4.c16 void exynos4_jpeg_sw_reset(void __iomem *base) in exynos4_jpeg_sw_reset() argument
20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
22 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
25 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
29 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset()
32 void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode() argument
36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
41 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode()
45 base in exynos4_jpeg_set_enc_dec_mode()
52 __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, unsigned int version) __exynos4_jpeg_set_img_fmt() argument
136 __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, unsigned int version) __exynos4_jpeg_set_enc_out_fmt() argument
169 exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) exynos4_jpeg_set_interrupt() argument
183 exynos4_jpeg_get_int_status(void __iomem *base) exynos4_jpeg_get_int_status() argument
188 exynos4_jpeg_get_fifo_status(void __iomem *base) exynos4_jpeg_get_fifo_status() argument
193 exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) exynos4_jpeg_set_huf_table_enable() argument
207 exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) exynos4_jpeg_set_sys_int_enable() argument
219 exynos4_jpeg_set_stream_buf_address(void __iomem *base, unsigned int address) exynos4_jpeg_set_stream_buf_address() argument
225 exynos4_jpeg_set_stream_size(void __iomem *base, unsigned int x_value, unsigned int y_value) exynos4_jpeg_set_stream_size() argument
233 exynos4_jpeg_set_frame_buf_address(void __iomem *base, struct s5p_jpeg_addr *exynos4_jpeg_addr) exynos4_jpeg_set_frame_buf_address() argument
241 exynos4_jpeg_set_encode_tbl_select(void __iomem *base, enum exynos4_jpeg_img_quality_level level) exynos4_jpeg_set_encode_tbl_select() argument
255 exynos4_jpeg_set_dec_components(void __iomem *base, int n) exynos4_jpeg_set_dec_components() argument
265 exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x) exynos4_jpeg_select_dec_q_tbl() argument
275 exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x) exynos4_jpeg_select_dec_h_tbl() argument
285 exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt) exynos4_jpeg_set_encode_hoff_cnt() argument
293 exynos4_jpeg_get_stream_size(void __iomem *base) exynos4_jpeg_get_stream_size() argument
298 exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size) exynos4_jpeg_set_dec_bitstream_size() argument
303 exynos4_jpeg_get_frame_size(void __iomem *base, unsigned int *width, unsigned int *height) exynos4_jpeg_get_frame_size() argument
312 exynos4_jpeg_get_frame_fmt(void __iomem *base) exynos4_jpeg_get_frame_fmt() argument
318 exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size) exynos4_jpeg_set_timer_count() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm_8960.c14 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
16 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
20 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base in dsi_28nm_dphy_set_timing()
44 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_init() local
56 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_ctrl() local
67 void __iomem *base = phy->reg_base; dsi_28nm_phy_calibration() local
97 void __iomem *base = phy->base; dsi_28nm_phy_lane_config() local
124 void __iomem *base = phy->base; dsi_28nm_phy_enable() local
[all...]

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