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Searched refs:bank_reg (Results 1 - 15 of 15) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-aspeed-sgpio.c99 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() function
187 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
206 addr_r = bank_reg(gpio, bank, reg_rdata); in sgpio_set_value()
207 addr_w = bank_reg(gpio, bank, reg_val); in sgpio_set_value()
286 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_sgpio_irq_ack()
305 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_sgpio_irq_set_mask()
368 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_sgpio_set_type()
373 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_sgpio_set_type()
378 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_sgpio_set_type()
403 reg = ioread32(bank_reg(dat in aspeed_sgpio_irq_handler()
[all...]
H A Dgpio-aspeed.c208 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, in bank_reg() function
309 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); in aspeed_gpio_change_cmd_source()
310 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); in aspeed_gpio_change_cmd_source()
356 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); in aspeed_gpio_copro_request()
386 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); in aspeed_gpio_get()
397 addr = bank_reg(gpio, bank, reg_val); in __aspeed_gpio_set()
430 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_in()
458 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_out()
497 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); in aspeed_gpio_get_direction()
540 status_addr = bank_reg(gpi in aspeed_gpio_irq_ack()
[all...]
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-aspeed-sgpio.c104 static void __iomem *bank_reg(struct aspeed_sgpio *gpio, in bank_reg() function
180 rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); in aspeed_sgpio_get()
199 addr_r = bank_reg(gpio, bank, reg_rdata); in sgpio_set_value()
200 addr_w = bank_reg(gpio, bank, reg_val); in sgpio_set_value()
279 status_addr = bank_reg(gpio, bank, reg_irq_status); in aspeed_sgpio_irq_ack()
298 addr = bank_reg(gpio, bank, reg_irq_enable); in aspeed_sgpio_irq_set_mask()
371 addr = bank_reg(gpio, bank, reg_irq_type0); in aspeed_sgpio_set_type()
376 addr = bank_reg(gpio, bank, reg_irq_type1); in aspeed_sgpio_set_type()
381 addr = bank_reg(gpio, bank, reg_irq_type2); in aspeed_sgpio_set_type()
406 reg = ioread32(bank_reg(dat in aspeed_sgpio_irq_handler()
[all...]
H A Dgpio-aspeed.c210 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, in bank_reg() function
311 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); in aspeed_gpio_change_cmd_source()
312 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); in aspeed_gpio_change_cmd_source()
358 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); in aspeed_gpio_copro_request()
388 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); in aspeed_gpio_get()
399 addr = bank_reg(gpio, bank, reg_val); in __aspeed_gpio_set()
432 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_in()
460 void __iomem *addr = bank_reg(gpio, bank, reg_dir); in aspeed_gpio_dir_out()
499 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); in aspeed_gpio_get_direction()
542 status_addr = bank_reg(gpi in aspeed_gpio_irq_ack()
[all...]
/kernel/linux/linux-5.10/drivers/i2c/
H A Di2c-stub.c47 static u8 bank_reg[MAX_CHIPS]; variable
48 module_param_array(bank_reg, byte, NULL, S_IRUGO);
49 MODULE_PARM_DESC(bank_reg, "Bank register");
77 u8 bank_reg; member
177 if (chip->bank_words && command == chip->bank_reg) { in stub_xfer()
321 chip->bank_reg = bank_reg[i]; in i2c_stub_allocate_banks()
/kernel/linux/linux-6.6/drivers/i2c/
H A Di2c-stub.c46 static u8 bank_reg[MAX_CHIPS]; variable
47 module_param_array(bank_reg, byte, NULL, S_IRUGO);
48 MODULE_PARM_DESC(bank_reg, "Bank register");
76 u8 bank_reg; member
176 if (chip->bank_words && command == chip->bank_reg) { in stub_xfer()
320 chip->bank_reg = bank_reg[i]; in i2c_stub_allocate_banks()
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
H A Diotiming-s3c2410.c53 * bank_reg - convert bank number to pointer to the control register.
56 static inline void __iomem *bank_reg(unsigned int bank) in bank_reg() function
366 bankcon = __raw_readl(bank_reg(bank)); in s3c2410_iotiming_calc()
412 __raw_writel(bt->bankcon, bank_reg(bank)); in s3c2410_iotiming_set()
444 bankcon = __raw_readl(bank_reg(bank)); in s3c2410_iotiming_get()
/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Dclk-rcg.c73 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_get_parent()
213 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in configure_bank()
253 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, in configure_bank()
280 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in configure_bank()
284 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); in configure_bank()
300 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_set_parent()
376 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_recalc_rate()
452 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_determine_rate()
H A Dclk-rcg.h103 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
113 u32 bank_reg; member
H A Dgcc-ipq806x.c2300 .bank_reg = 0x3ca0,
2372 .bank_reg = 0x3ca0,
2444 .bank_reg = 0x3ce0,
2516 .bank_reg = 0x3d00,
2592 .bank_reg = 0x3dc0,
2654 .bank_reg = 0x3d20,
2707 .bank_reg = 0x3d40,
H A Dmmcc-msm8960.c806 .bank_reg = 0x0060,
866 .bank_reg = 0x0074,
967 .bank_reg = 0x0080,
1045 .bank_reg = 0x0178,
1252 .bank_reg = 0x00c0,
1359 .bank_reg = 0x00e8,
1585 .bank_reg = 0x00f8,
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dclk-rcg.c73 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_get_parent()
213 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in configure_bank()
253 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, in configure_bank()
280 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in configure_bank()
284 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); in configure_bank()
300 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_set_parent()
376 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_recalc_rate()
452 regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg); in clk_dyn_rcg_determine_rate()
H A Dclk-rcg.h104 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
114 u32 bank_reg; member
H A Dgcc-ipq806x.c2423 .bank_reg = 0x3ca0,
2495 .bank_reg = 0x3ca0,
2567 .bank_reg = 0x3ce0,
2639 .bank_reg = 0x3d00,
2715 .bank_reg = 0x3dc0,
2785 .bank_reg = 0x3d20,
2838 .bank_reg = 0x3d40,
2895 .bank_reg = 0x36C0,
2955 .bank_reg = 0x3d80,
3015 .bank_reg
[all...]
H A Dmmcc-msm8960.c832 .bank_reg = 0x0060,
894 .bank_reg = 0x0074,
997 .bank_reg = 0x0080,
1077 .bank_reg = 0x0178,
1292 .bank_reg = 0x00c0,
1405 .bank_reg = 0x00e8,
1645 .bank_reg = 0x00f8,

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