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Searched refs:MMU (Results 1 - 25 of 48) sorted by relevance

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/kernel/linux/linux-6.6/drivers/accel/ivpu/
H A Divpu_mmu.c213 return "MMU bypass is disallowed for this StreamID"; in ivpu_mmu_event_to_str()
255 ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
259 ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF); in ivpu_mmu_config_check()
263 ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF); in ivpu_mmu_config_check()
274 ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref); in ivpu_mmu_config_check()
287 ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size); in ivpu_mmu_cdtab_alloc()
306 ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n", in ivpu_mmu_strtab_alloc()
325 ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_cmdq_alloc()
344 ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n", in ivpu_mmu_evtq_alloc()
421 ivpu_err(vdev, "Failed to write MMU CM in ivpu_mmu_cmdq_cmd_write()
[all...]
/kernel/linux/linux-5.10/arch/arc/include/asm/
H A Dtlb-mmu1.h20 ; Calculate set index for 2-way MMU
21 ; -avoiding use of GetIndex from MMU
45 ; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
52 and.f r0,r0,0x000fe000 /* 2-way MMU mask */
91 lr r1,[ARC_REG_TLBINDEX] /* r1 = index where MMU wants to put data */
/kernel/linux/linux-5.10/arch/arm/boot/compressed/
H A Dhead-xscale.S30 @ disabling MMU and caches
32 bic r0, r0, #0x05 @ clear DC, MMU
H A Dhead.S275 * without the MMU on, we are in the physical address space.
833 * ?? ARMv3 MMU does not allow reading the control register,
954 orrne r0, r0, #1 @ MMU enabled
1211 * Turn off the Cache and MMU. ARMv3 does not support
1245 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1259 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1547 bic r0, r0, #0x5 @ disable MMU and caches
1558 bl cache_clean_flush @ may run with the MMU off
1563 @ since it mandates that the MMU and caches are on, with all
1568 @ anyway, with the MMU an
[all...]
/kernel/linux/linux-6.6/arch/arm/boot/compressed/
H A Dhead-sa1100.S40 @ disabling MMU and caches
42 bic r0, r0, #0x0d @ clear WB, DC, MMU
H A Dhead-xscale.S30 @ disabling MMU and caches
32 bic r0, r0, #0x05 @ clear DC, MMU
H A Dhead.S264 * without the MMU on, we are in the physical address space.
773 * ?? ARMv3 MMU does not allow reading the control register,
890 orrne r0, r0, #1 @ MMU enabled
1147 * Turn off the Cache and MMU. ARMv3 does not support
1181 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1195 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1447 bic r0, r0, #0x5 @ disable MMU and caches
1458 bl cache_clean_flush @ may run with the MMU off
1463 @ since it mandates that the MMU and caches are on, with all
1468 @ anyway, with the MMU an
[all...]
/kernel/linux/linux-5.10/arch/arm/mm/
H A Dpv-fixup-asm.S23 bic ip, r8, #CR_M @ disable caches and MMU
80 mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
/kernel/linux/linux-6.6/arch/arm/mm/
H A Dpv-fixup-asm.S23 bic ip, r8, #CR_M @ disable caches and MMU
80 mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
/kernel/linux/linux-5.10/arch/arc/mm/
H A Dtlbex.S8 * -MMU v1: moved out legacy code into a seperate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
98 ; VERIFY if the ASID in MMU-PID Reg is same as
156 ; we use the MMU PID Reg to get current ASID.
172 and r2, r0, 0xFF ; MMU PID bits only for comparison
272 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
279 ; Commit the TLB entry into MMU
379 ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
381 ; But only for old MMU o
[all...]
/kernel/linux/linux-5.10/arch/nios2/
H A DMakefile21 export MMU
/kernel/linux/linux-6.6/arch/nios2/
H A DMakefile20 export MMU
/kernel/linux/linux-5.10/scripts/
H A Dchecksyscalls.sh54 /* MMU */
/kernel/linux/linux-5.10/arch/microblaze/kernel/
H A DMakefile30 obj-y += entry$(MMU).o
/kernel/linux/linux-6.6/scripts/
H A Dchecksyscalls.sh58 /* MMU */
/kernel/linux/linux-5.10/drivers/infiniband/hw/hfi1/
H A Dtrace_dbg.h129 __hfi1_trace_def(MMU); variable
/kernel/linux/linux-6.6/drivers/infiniband/hw/hfi1/
H A Dtrace_dbg.h91 __hfi1_trace_def(MMU); variable
/kernel/linux/linux-5.10/arch/sparc/kernel/
H A Detrap_32.S217 /* Call MMU-architecture dependent stack checking
238 LEON_PI( lda [%g0] ASI_LEON_MMUREGS, %glob_tmp) ! read MMU control
239 SUN_PI_( lda [%g0] ASI_M_MMUREGS, %glob_tmp) ! read MMU control
H A Dwof.S318 * We disable fault traps in the MMU control register,
339 LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %glob_tmp) ! read MMU control
340 SUN_PI_(lda [%g0] ASI_M_MMUREGS, %glob_tmp) ! read MMU control
/kernel/linux/linux-6.6/arch/sparc/kernel/
H A Detrap_32.S217 /* Call MMU-architecture dependent stack checking
238 LEON_PI( lda [%g0] ASI_LEON_MMUREGS, %glob_tmp) ! read MMU control
239 SUN_PI_( lda [%g0] ASI_M_MMUREGS, %glob_tmp) ! read MMU control
H A Dwof.S318 * We disable fault traps in the MMU control register,
339 LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %glob_tmp) ! read MMU control
340 SUN_PI_(lda [%g0] ASI_M_MMUREGS, %glob_tmp) ! read MMU control
/kernel/linux/linux-5.10/arch/arm/mach-mvebu/
H A Dcoherency_ll.S33 tst r1, #CR_M @ Check MMU bit enabled
37 * MMU is disabled, use the physical address of the coherency
44 * MMU is enabled, use the virtual address of the coherency
73 * MMU can be disabled. The Armada XP SoC has an exclusive monitor
75 * that, exclusive transactions are functional even when the MMU is
/kernel/linux/linux-5.10/arch/arm/include/debug/
H A Dsa1100.S19 tst \rp, #1 @ MMU enabled?
/kernel/linux/linux-6.6/arch/arm/include/debug/
H A Dsa1100.S19 tst \rp, #1 @ MMU enabled?
/kernel/linux/linux-6.6/arch/arm/mach-mvebu/
H A Dcoherency_ll.S31 tst r1, #CR_M @ Check MMU bit enabled
35 * MMU is disabled, use the physical address of the coherency
44 * MMU is enabled, use the virtual address of the coherency
73 * MMU can be disabled. The Armada XP SoC has an exclusive monitor
75 * that, exclusive transactions are functional even when the MMU is

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