Lines Matching refs:MMU
264 * without the MMU on, we are in the physical address space.
773 * ?? ARMv3 MMU does not allow reading the control register,
890 orrne r0, r0, #1 @ MMU enabled
1147 * Turn off the Cache and MMU. ARMv3 does not support
1181 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1195 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1447 bic r0, r0, #0x5 @ disable MMU and caches
1458 bl cache_clean_flush @ may run with the MMU off
1463 @ since it mandates that the MMU and caches are on, with all
1468 @ anyway, with the MMU and caches either on or off.
1477 tst r1, #0x1 @ MMU enabled at HYP?
1485 @ will disable the MMU before jumping to the kernel proper.
1509 tst r0, #0x1 @ MMU enabled?