Lines Matching refs:MMU
8 * -MMU v1: moved out legacy code into a seperate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
98 ; VERIFY if the ASID in MMU-PID Reg is same as
156 ; we use the MMU PID Reg to get current ASID.
172 and r2, r0, 0xFF ; MMU PID bits only for comparison
272 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
279 ; Commit the TLB entry into MMU
379 ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
381 ; But only for old MMU or one with Metal Fix