Lines Matching refs:MMU
275 * without the MMU on, we are in the physical address space.
833 * ?? ARMv3 MMU does not allow reading the control register,
954 orrne r0, r0, #1 @ MMU enabled
1211 * Turn off the Cache and MMU. ARMv3 does not support
1245 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1259 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1547 bic r0, r0, #0x5 @ disable MMU and caches
1558 bl cache_clean_flush @ may run with the MMU off
1563 @ since it mandates that the MMU and caches are on, with all
1568 @ anyway, with the MMU and caches either on or off.
1577 tst r1, #0x1 @ MMU enabled at HYP?
1585 @ will disable the MMU before jumping to the kernel proper.
1609 tst r0, #0x1 @ MMU enabled?