Lines Matching refs:MMU
213 return "MMU bypass is disallowed for this StreamID";
255 ivpu_dbg(vdev, MMU, "IDR0 0x%x != IDR0_REF 0x%x\n", val, val_ref);
259 ivpu_dbg(vdev, MMU, "IDR1 0x%x != IDR1_REF 0x%x\n", val, IVPU_MMU_IDR1_REF);
263 ivpu_dbg(vdev, MMU, "IDR3 0x%x != IDR3_REF 0x%x\n", val, IVPU_MMU_IDR3_REF);
274 ivpu_dbg(vdev, MMU, "IDR5 0x%x != IDR5_REF 0x%x\n", val, val_ref);
287 ivpu_dbg(vdev, MMU, "CDTAB alloc: dma=%pad size=%zu\n", &cdtab->dma, size);
306 ivpu_dbg(vdev, MMU, "STRTAB alloc: dma=%pad dma_q=%pad size=%zu\n",
325 ivpu_dbg(vdev, MMU, "CMDQ alloc: dma=%pad dma_q=%pad size=%u\n",
344 ivpu_dbg(vdev, MMU, "EVTQ alloc: dma=%pad dma_q=%pad size=%u\n",
421 ivpu_err(vdev, "Failed to write MMU CMD %s\n", name);
429 ivpu_dbg(vdev, MMU, "CMD write: %s data: 0x%llx 0x%llx\n", name, data0, data1);
585 ivpu_dbg(vdev, MMU, "STRTAB write entry (SSID=%u): 0x%llx, 0x%llx\n", sid, str[0], str[1]);
659 ivpu_dbg(vdev, MMU, "CDTAB %s entry (SSID=%u, dma=%pad): 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",
708 ivpu_dbg(vdev, MMU, "Init..\n");
731 ivpu_err(vdev, "Failed to resume MMU: %d\n", ret);
735 ivpu_dbg(vdev, MMU, "Init done\n");
751 ivpu_err(vdev, "Failed to reset MMU: %d\n", ret);
793 ivpu_err(vdev, "MMU EVTQ: 0x%x (%s) SSID: %d SID: %d, e[2] %08x, e[3] %08x, in addr: 0x%llx, fetch addr: 0x%llx\n",
819 ivpu_dbg(vdev, IRQ, "MMU event queue\n");
839 ivpu_dbg(vdev, IRQ, "MMU error\n");
849 ivpu_warn_ratelimited(vdev, "MMU MSI ABT write aborted\n");
852 ivpu_warn_ratelimited(vdev, "MMU PRIQ MSI ABT write aborted\n");
855 ivpu_warn_ratelimited(vdev, "MMU EVTQ MSI ABT write aborted\n");
858 ivpu_warn_ratelimited(vdev, "MMU CMDQ MSI ABT write aborted\n");
861 ivpu_err_ratelimited(vdev, "MMU PRIQ write aborted\n");
864 ivpu_err_ratelimited(vdev, "MMU EVTQ write aborted\n");
867 ivpu_err_ratelimited(vdev, "MMU CMDQ write aborted\n");