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Searched refs:fbits (Results 1 - 25 of 25) sorted by relevance

/third_party/vixl/test/aarch64/
H A Dtest-assembler-fp-aarch64.cc4594 // value. All possible values of 'fbits' are tested. The expected value is
4645 // Test all possible values of fbits.
4646 for (int fbits = 1; fbits <= 32; fbits++) {
4647 __ Scvtf(d0, x10, fbits);
4648 __ Ucvtf(d1, x10, fbits);
4649 __ Scvtf(d2, w11, fbits);
4650 __ Ucvtf(d3, w11, fbits);
4651 __ Str(d0, MemOperand(x0, fbits * kDRegSizeInByte
[all...]
H A Dtest-simulator-aarch64.cc201 int fbits);
204 int fbits);
1021 for (unsigned fbits = 0; fbits <= d_size; ++fbits) { in TestFPToFixed_Helper()
1024 (masm.*helper)(rd, fn, fbits); in TestFPToFixed_Helper()
1330 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedS()
1338 fbits, in TestFPToFixedS()
[all...]
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.cc2816 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in scvtf() argument
2817 DCHECK_GE(fbits, 0); in scvtf()
2818 if (fbits == 0) { in scvtf()
2822 NEONShiftRightImmediate(vd, vn, fbits, NEON_SCVTF_imm); in scvtf()
2826 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf() argument
2827 DCHECK_GE(fbits, 0); in ucvtf()
2828 if (fbits == 0) { in ucvtf()
2832 NEONShiftRightImmediate(vd, vn, fbits, NEON_UCVTF_imm); in ucvtf()
2836 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf() argument
2837 DCHECK_GE(fbits, in scvtf()
2846 ucvtf(const VRegister& fd, const Register& rn, int fbits) ucvtf() argument
2967 fcvtzs(const Register& rd, const VRegister& vn, int fbits) fcvtzs() argument
2978 fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) fcvtzs() argument
2988 fcvtzu(const Register& rd, const VRegister& vn, int fbits) fcvtzu() argument
2999 fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) fcvtzu() argument
[all...]
H A Dmacro-assembler-arm64.h1023 void Fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Fcvtzs()
1025 fcvtzs(vd, vn, fbits); in Fcvtzs()
1035 void Fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Fcvtzu()
1037 fcvtzu(vd, vn, fbits); in Fcvtzu()
1132 unsigned fbits = 0);
1133 void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Scvtf()
1135 scvtf(vd, vn, fbits); in Scvtf()
1138 unsigned fbits = 0);
1139 void Ucvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Ucvtf()
1141 ucvtf(vd, vn, fbits); in Ucvtf()
[all...]
H A Dassembler-arm64.h1766 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0);
1769 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0);
1772 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0);
1775 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0);
1790 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0);
1793 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0);
1796 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
1799 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
H A Dmacro-assembler-arm64-inl.h912 unsigned fbits) { in Scvtf()
914 scvtf(fd, rn, fbits); in Scvtf()
992 unsigned fbits) { in Ucvtf()
994 ucvtf(fd, rn, fbits); in Ucvtf()
911 Scvtf(const VRegister& fd, const Register& rn, unsigned fbits) Scvtf() argument
991 Ucvtf(const VRegister& fd, const Register& rn, unsigned fbits) Ucvtf() argument
/third_party/python/Objects/
H A Dfloatobject.c2181 unsigned int fbits; in PyFloat_Pack4() local
2224 fbits = (unsigned int)(f + 0.5); /* Round */ in PyFloat_Pack4()
2225 assert(fbits <= 8388608); in PyFloat_Pack4()
2226 if (fbits >> 23) { in PyFloat_Pack4()
2228 fbits = 0; in PyFloat_Pack4()
2239 *p = (char) (((e & 1) << 7) | (fbits >> 16)); in PyFloat_Pack4()
2243 *p = (fbits >> 8) & 0xFF; in PyFloat_Pack4()
2247 *p = fbits & 0xFF; in PyFloat_Pack4()
/third_party/vixl/src/aarch64/
H A Dlogic-aarch64.cc87 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble() argument
89 return UFixedToDouble(src, fbits, round); in FixedToDouble()
91 return -UFixedToDouble(src, fbits, round); in FixedToDouble()
93 return -UFixedToDouble(-src, fbits, round); in FixedToDouble()
98 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble() argument
108 const int64_t exponent = highest_significant_bit - fbits; in UFixedToDouble()
114 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat() argument
116 return UFixedToFloat(src, fbits, round); in FixedToFloat()
118 return -UFixedToFloat(src, fbits, round); in FixedToFloat()
120 return -UFixedToFloat(-src, fbits, roun in FixedToFloat()
125 UFixedToFloat(uint64_t src, int fbits, FPRounding round) UFixedToFloat() argument
141 FixedToFloat16(int64_t src, int fbits, FPRounding round) FixedToFloat16() argument
152 UFixedToFloat16(uint64_t src, int fbits, FPRounding round) UFixedToFloat16() argument
[all...]
H A Dassembler-aarch64.cc3702 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) {
3706 VIXL_ASSERT((fbits >= 0) && (fbits <= rd.GetSizeInBits()));
3707 if (fbits == 0) {
3710 Emit(SF(rd) | FPType(vn) | FCVTZS_fixed | FPScale(64 - fbits) | Rn(vn) |
3716 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) {
3720 VIXL_ASSERT(fbits >= 0);
3721 if (fbits == 0) {
3730 NEONShiftRightImmediate(vd, vn, fbits, NEON_FCVTZS_imm);
3735 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) {
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H A Dsimulator-aarch64.h4139 int fbits = 0);
4143 int fbits,
4152 int fbits = 0);
4156 int fbits,
4674 int fbits = 0);
4679 int fbits = 0);
4687 int fbits = 0);
4692 int fbits = 0);
4835 R FPToFixed(T op, int fbits, bool is_signed, FPRounding rounding);
4845 double FixedToDouble(int64_t src, int fbits, FPRoundin
[all...]
H A Dsimulator-aarch64.cc6077 int fbits = 64 - instr->GetFPScale(); in Simulator() local
6085 WriteDRegister(dst, FixedToDouble(ReadXRegister(src), fbits, round)); in Simulator()
6088 WriteDRegister(dst, FixedToDouble(ReadWRegister(src), fbits, round)); in Simulator()
6091 WriteDRegister(dst, UFixedToDouble(ReadXRegister(src), fbits, round)); in Simulator()
6095 UFixedToDouble(ReadRegister<uint32_t>(src), fbits, round)); in Simulator()
6099 WriteSRegister(dst, FixedToFloat(ReadXRegister(src), fbits, round)); in Simulator()
6102 WriteSRegister(dst, FixedToFloat(ReadWRegister(src), fbits, round)); in Simulator()
6105 WriteSRegister(dst, UFixedToFloat(ReadXRegister(src), fbits, round)); in Simulator()
6109 UFixedToFloat(ReadRegister<uint32_t>(src), fbits, round)); in Simulator()
6113 WriteHRegister(dst, FixedToFloat16(ReadXRegister(src), fbits, roun in Simulator()
[all...]
H A Dmacro-assembler-aarch64.h1605 void Fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) { in Fcvtzs()
1609 fcvtzs(rd, vn, fbits); in Fcvtzs()
1617 void Fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) { in Fcvtzu()
1621 fcvtzu(rd, vn, fbits); in Fcvtzu()
2431 void Scvtf(const VRegister& vd, const Register& rn, int fbits = 0) { in Scvtf()
2435 scvtf(vd, rn, fbits); in Scvtf()
2723 void Ucvtf(const VRegister& vd, const Register& rn, int fbits = 0) { in Ucvtf()
2727 ucvtf(vd, rn, fbits); in Ucvtf()
3496 void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) { in Scvtf()
3499 scvtf(vd, vn, fbits); in Scvtf()
[all...]
H A Dassembler-aarch64.h2452 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0);
2455 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0);
2458 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0);
2461 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0);
2476 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0);
2479 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0);
2482 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
2485 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
/third_party/ffmpeg/libavcodec/
H A Dopus_silk.c164 int fbits; // fractional bits used for the gain in silk_is_lpc_stable() local
178 fbits = opus_ilog(gaindiv); in silk_is_lpc_stable()
179 gain = ((1 << 29) - 1) / (gaindiv >> (fbits + 1 - 16)); // Q<fbits-16> in silk_is_lpc_stable()
180 error = (1 << 29) - MULL(gaindiv << (15 + 16 - fbits), gain, 16); in silk_is_lpc_stable()
189 int64_t tmp = ROUND_MULL(x, gain, fbits); in silk_is_lpc_stable()
H A Dmlpenc.c68 uint8_t fbits[MAX_CHANNELS]; ///< fraction bits member
271 if (prev->fbits[channel] != mp->fbits[channel]) in compare_matrix_params()
367 dst->fbits[channel] = src->fbits[channel]; in copy_matrix_params()
804 put_bits(pb, 4, mp->fbits[mat]); in write_matrix_params()
813 coeff >>= 14 - mp->fbits[mat]; in write_matrix_params()
815 put_sbits(pb, mp->fbits[mat] + 2, coeff); in write_matrix_params()
1412 mp->fbits [mat] = 14 - bits; in code_matrix_coeffs()
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc41 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble() argument
43 return UFixedToDouble(src, fbits, round); in FixedToDouble()
45 return -UFixedToDouble(src, fbits, round); in FixedToDouble()
47 return -UFixedToDouble(-src, fbits, round); in FixedToDouble()
51 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble() argument
61 const int64_t exponent = highest_significant_bit - fbits; in UFixedToDouble()
66 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat() argument
68 return UFixedToFloat(src, fbits, round); in FixedToFloat()
70 return -UFixedToFloat(src, fbits, round); in FixedToFloat()
72 return -UFixedToFloat(-src, fbits, roun in FixedToFloat()
76 UFixedToFloat(uint64_t src, int fbits, FPRounding round) UFixedToFloat() argument
3758 fcvts(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, int fbits) fcvts() argument
3777 fcvtu(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, FPRounding rounding_mode, int fbits) fcvtu() argument
4195 scvtf(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int fbits, FPRounding round) scvtf() argument
4211 ucvtf(VectorFormat vform, LogicVRegister dst, const LogicVRegister& src, int fbits, FPRounding round) ucvtf() argument
[all...]
H A Dsimulator-arm64.h1892 const LogicVRegister& src, int fbits,
1895 const LogicVRegister& src, int fbits,
2134 int fbits = 0);
2137 int fbits = 0);
2180 R FPToFixed(T op, int fbits, bool is_signed, FPRounding rounding);
2193 double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
2194 double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode);
2195 float FixedToFloat(int64_t src, int fbits, FPRounding round_mode);
2196 float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode);
H A Dsimulator-arm64.cc3013 int fbits = 64 - instr->FPScale();
3021 set_dreg(dst, FixedToDouble(xreg(src), fbits, round));
3024 set_dreg(dst, FixedToDouble(wreg(src), fbits, round));
3027 set_dreg(dst, UFixedToDouble(xreg(src), fbits, round));
3030 set_dreg(dst, UFixedToDouble(reg<uint32_t>(src), fbits, round));
3034 set_sreg(dst, FixedToFloat(xreg(src), fbits, round));
3037 set_sreg(dst, FixedToFloat(wreg(src), fbits, round));
3040 set_sreg(dst, UFixedToFloat(xreg(src), fbits, round));
3043 set_sreg(dst, UFixedToFloat(reg<uint32_t>(src), fbits, round));
/third_party/vixl/src/aarch32/
H A Dassembler-aarch32.cc16315 int32_t fbits) { in vcvt()
16322 // VCVT{<c>}{<q>}.<dt>.<dt> <Dd>, <Dm>, #<fbits> ; T1 in vcvt()
16323 if (encoded_dt.IsValid() && (fbits >= 1) && (fbits <= 32)) { in vcvt()
16325 uint32_t fbits_ = 64 - fbits; in vcvt()
16333 // VCVT{<c>}{<q>}.F64.<dt> <Ddm>, <Ddm>, #<fbits> ; T1 in vcvt()
16335 (((dt2.Is(S16) || dt2.Is(U16)) && (fbits <= 16)) || in vcvt()
16336 ((dt2.Is(S32) || dt2.Is(U32)) && (fbits >= 1) && (fbits <= 32)))) { in vcvt()
16341 uint32_t fbits_ = offset - fbits; in vcvt()
16310 vcvt(Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) vcvt() argument
16414 vcvt(Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) vcvt() argument
16450 vcvt(Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) vcvt() argument
[all...]
H A Dassembler-aarch32.h426 int32_t fbits);
432 int32_t fbits);
438 int32_t fbits);
1312 int32_t /*fbits*/) { in Delegate()
1324 int32_t /*fbits*/) { in Delegate()
1336 int32_t /*fbits*/) { in Delegate()
4245 int32_t fbits);
4247 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in vcvt()
4248 vcvt(al, dt1, dt2, rd, rm, fbits); in vcvt()
4256 int32_t fbits);
4246 vcvt( DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) vcvt() argument
4257 vcvt( DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) vcvt() argument
4268 vcvt( DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) vcvt() argument
[all...]
H A Dmacro-assembler-aarch32.h7691 int32_t fbits) { in MacroAssembler()
7702 vcvt(cond, dt1, dt2, rd, rm, fbits); in MacroAssembler()
7705 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in MacroAssembler()
7706 Vcvt(al, dt1, dt2, rd, rm, fbits); in MacroAssembler()
7714 int32_t fbits) { in MacroAssembler()
7725 vcvt(cond, dt1, dt2, rd, rm, fbits); in MacroAssembler()
7728 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in MacroAssembler()
7729 Vcvt(al, dt1, dt2, rd, rm, fbits); in MacroAssembler()
7737 int32_t fbits) { in MacroAssembler()
7748 vcvt(cond, dt1, dt2, rd, rm, fbits); in MacroAssembler()
7686 Vcvt(Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) MacroAssembler() argument
7704 Vcvt( DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) MacroAssembler() argument
7709 Vcvt(Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) MacroAssembler() argument
7727 Vcvt( DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) MacroAssembler() argument
7732 Vcvt(Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) MacroAssembler() argument
7750 Vcvt( DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) MacroAssembler() argument
[all...]
H A Ddisasm-aarch32.h1699 int32_t fbits);
1706 int32_t fbits);
1713 int32_t fbits);
H A Ddisasm-aarch32.cc4428 int32_t fbits) { in vcvt()
4431 << " " << rd << ", " << rm << ", " << SignedImmediatePrinter(fbits); in vcvt()
4439 int32_t fbits) { in vcvt()
4442 << " " << rd << ", " << rm << ", " << SignedImmediatePrinter(fbits); in vcvt()
4450 int32_t fbits) { in vcvt()
4453 << " " << rd << ", " << rm << ", " << SignedImmediatePrinter(fbits); in vcvt()
4423 vcvt(Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) vcvt() argument
4434 vcvt(Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) vcvt() argument
4445 vcvt(Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) vcvt() argument
23878 uint32_t fbits = offset - (((instr >> 5) & 0x1) | DecodeT32() local
23886 fbits); DecodeT32() local
23956 uint32_t fbits = offset - (((instr >> 5) & 0x1) | DecodeT32() local
23964 fbits); DecodeT32() local
24224 uint32_t fbits = offset - (((instr >> 5) & 0x1) | DecodeT32() local
24232 fbits); DecodeT32() local
24302 uint32_t fbits = offset - (((instr >> 5) & 0x1) | DecodeT32() local
24310 fbits); DecodeT32() local
36096 uint32_t fbits = DecodeT32() local
36104 fbits); DecodeT32() local
38262 uint32_t fbits = DecodeT32() local
38270 fbits); DecodeT32() local
47736 uint32_t fbits = 64 - ((instr >> 16) & 0x3f); DecodeA32() local
49451 uint32_t fbits = 64 - ((instr >> 16) & 0x3f); DecodeA32() local
66523 uint32_t fbits = offset - (((instr >> 5) & 0x1) | DecodeA32() local
66626 uint32_t fbits = offset - (((instr >> 5) & 0x1) | DecodeA32() local
66971 uint32_t fbits = offset - (((instr >> 5) & 0x1) | DecodeA32() local
67074 uint32_t fbits = offset - (((instr >> 5) & 0x1) | DecodeA32() local
[all...]
/third_party/skia/third_party/skcms/
H A Dskcms.cc86 float fbits = (1.0f * (1<<23)) * (x + 121.274057500f in exp2f_() local
90 // Before we cast fbits to int32_t, check for out of range values to pacify UBSAN. in exp2f_()
94 if (fbits >= (float)INT_MAX) { in exp2f_()
96 } else if (fbits < 0) { in exp2f_()
100 int32_t bits = (int32_t)fbits; in exp2f_()
/third_party/skia/third_party/skcms/src/
H A DTransform_inl.h294 F fbits = (1.0f * (1<<23)) * (x + 121.274057500f in approx_exp2()
297 I32 bits = cast<I32>(max_(fbits, F0)); in approx_exp2()

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