Searched refs:__OM (Results 1 - 15 of 15) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm35p.h	304 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 501 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 552 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 558 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 560 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 561 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 562 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 563 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 564 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 565 __OM uint32_ [all...]
H A D	core_cm33.h	304 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 501 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 552 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 558 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 560 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 561 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 562 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 563 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 564 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 565 __OM uint32_ [all...]
H A D	core_cm7.h	254 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 448 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 496 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 502 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 504 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 505 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 506 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 507 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 508 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 509 __OM uint32_ [all...]
H A D	core_starmc1.h	315 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 512 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 564 __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ 570 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 572 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 573 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 574 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 575 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 576 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 577 __OM uint32_ [all...]
H A D	core_cm4.h	239 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 433 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 477 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 828 __OM union 830 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ 831 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ 832 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ 842 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ 1420 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
H A D	core_cm3.h	180 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 360 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 404 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 763 __OM union 765 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ 766 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ 767 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ 777 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ 1244 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
H A D	core_cm85.h	311 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 532 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 583 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 590 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 592 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 593 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 594 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 595 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 596 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 597 __OM uint32_ [all...]
H A D	core_cm55.h	311 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 511 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 562 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ 569 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ 571 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ 572 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ 573 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ 574 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ 575 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ 576 __OM uint32_ [all...]
H A D	core_sc300.h	180 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 360 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 746 __OM union 748 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */ 749 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */ 750 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */ 760 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */ 1227 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
H A D	core_ca.h	179 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ macro 697 __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ 757 __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ 759 __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ 761 __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ 763 __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ 780 __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ 967 __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ 972 __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ 981 __OM uint32_ [all...]
H A D	core_cm23.h	201 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro 1023 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 1133 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
H A D	core_sc000.h	180 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
H A D	core_cm1.h	170 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
H A D	core_cm0.h	170 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
H A D	core_cm0plus.h	180 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro

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Indexes created Thu Nov 07 10:32:03 CST 2024