1 /*
2 * Copyright (c) 2018-2023 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS Cortex-M35P Core Peripheral Access Layer Header File
21 */
22
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
29 #endif
30
31 #ifndef __CORE_CM35P_H_GENERIC
32 #define __CORE_CM35P_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M35P
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM35 definitions */
66
67 #define __CORTEX_M (35U) /*!< Cortex-M Core */
68
69 /** __FPU_USED indicates whether an FPU is used or not.
70 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
71 */
72 #if defined ( __CC_ARM )
73 #if defined (__TARGET_FPU_VFP)
74 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
75 #define __FPU_USED 1U
76 #else
77 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
78 #define __FPU_USED 0U
79 #endif
80 #else
81 #define __FPU_USED 0U
82 #endif
83
84 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
85 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
86 #define __DSP_USED 1U
87 #else
88 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
89 #define __DSP_USED 0U
90 #endif
91 #else
92 #define __DSP_USED 0U
93 #endif
94
95 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
96 #if defined (__ARM_FP)
97 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
98 #define __FPU_USED 1U
99 #else
100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101 #define __FPU_USED 0U
102 #endif
103 #else
104 #define __FPU_USED 0U
105 #endif
106
107 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
108 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
109 #define __DSP_USED 1U
110 #else
111 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
112 #define __DSP_USED 0U
113 #endif
114 #else
115 #define __DSP_USED 0U
116 #endif
117
118 #elif defined (__ti__)
119 #if defined (__ARM_FP)
120 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
121 #define __FPU_USED 1U
122 #else
123 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124 #define __FPU_USED 0U
125 #endif
126 #else
127 #define __FPU_USED 0U
128 #endif
129
130 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
131 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
132 #define __DSP_USED 1U
133 #else
134 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
135 #define __DSP_USED 0U
136 #endif
137 #else
138 #define __DSP_USED 0U
139 #endif
140
141 #elif defined ( __GNUC__ )
142 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
143 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
144 #define __FPU_USED 1U
145 #else
146 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
147 #define __FPU_USED 0U
148 #endif
149 #else
150 #define __FPU_USED 0U
151 #endif
152
153 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
154 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
155 #define __DSP_USED 1U
156 #else
157 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
158 #define __DSP_USED 0U
159 #endif
160 #else
161 #define __DSP_USED 0U
162 #endif
163
164 #elif defined ( __ICCARM__ )
165 #if defined (__ARMVFP__)
166 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
167 #define __FPU_USED 1U
168 #else
169 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
170 #define __FPU_USED 0U
171 #endif
172 #else
173 #define __FPU_USED 0U
174 #endif
175
176 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
177 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
178 #define __DSP_USED 1U
179 #else
180 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
181 #define __DSP_USED 0U
182 #endif
183 #else
184 #define __DSP_USED 0U
185 #endif
186
187 #elif defined ( __TI_ARM__ )
188 #if defined (__TI_VFP_SUPPORT__)
189 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
190 #define __FPU_USED 1U
191 #else
192 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
193 #define __FPU_USED 0U
194 #endif
195 #else
196 #define __FPU_USED 0U
197 #endif
198
199 #elif defined ( __TASKING__ )
200 #if defined (__FPU_VFP__)
201 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
202 #define __FPU_USED 1U
203 #else
204 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
205 #define __FPU_USED 0U
206 #endif
207 #else
208 #define __FPU_USED 0U
209 #endif
210
211 #elif defined ( __CSMC__ )
212 #if ( __CSMC__ & 0x400U)
213 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
214 #define __FPU_USED 1U
215 #else
216 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
217 #define __FPU_USED 0U
218 #endif
219 #else
220 #define __FPU_USED 0U
221 #endif
222
223 #endif
224
225 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
226
227
228 #ifdef __cplusplus
229 }
230 #endif
231
232 #endif /* __CORE_CM35P_H_GENERIC */
233
234 #ifndef __CMSIS_GENERIC
235
236 #ifndef __CORE_CM35P_H_DEPENDANT
237 #define __CORE_CM35P_H_DEPENDANT
238
239 #ifdef __cplusplus
240 extern "C" {
241 #endif
242
243 /* check device defines and use defaults */
244 #if defined __CHECK_DEVICE_DEFINES
245 #ifndef __CM35P_REV
246 #define __CM35P_REV 0x0000U
247 #warning "__CM35P_REV not defined in device header file; using default!"
248 #endif
249
250 #ifndef __FPU_PRESENT
251 #define __FPU_PRESENT 0U
252 #warning "__FPU_PRESENT not defined in device header file; using default!"
253 #endif
254
255 #ifndef __MPU_PRESENT
256 #define __MPU_PRESENT 0U
257 #warning "__MPU_PRESENT not defined in device header file; using default!"
258 #endif
259
260 #ifndef __SAUREGION_PRESENT
261 #define __SAUREGION_PRESENT 0U
262 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
263 #endif
264
265 #ifndef __DSP_PRESENT
266 #define __DSP_PRESENT 0U
267 #warning "__DSP_PRESENT not defined in device header file; using default!"
268 #endif
269
270 #ifndef __VTOR_PRESENT
271 #define __VTOR_PRESENT 1U
272 #warning "__VTOR_PRESENT not defined in device header file; using default!"
273 #endif
274
275 #ifndef __NVIC_PRIO_BITS
276 #define __NVIC_PRIO_BITS 3U
277 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
278 #endif
279
280 #ifndef __Vendor_SysTickConfig
281 #define __Vendor_SysTickConfig 0U
282 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
283 #endif
284 #endif
285
286 /* IO definitions (access restrictions to peripheral registers) */
287 /**
288 \defgroup CMSIS_glob_defs CMSIS Global Defines
289
290 <strong>IO Type Qualifiers</strong> are used
291 \li to specify the access to peripheral variables.
292 \li for automatic generation of peripheral register debug information.
293 */
294 #ifdef __cplusplus
295 #define __I volatile /*!< Defines 'read only' permissions */
296 #else
297 #define __I volatile const /*!< Defines 'read only' permissions */
298 #endif
299 #define __O volatile /*!< Defines 'write only' permissions */
300 #define __IO volatile /*!< Defines 'read / write' permissions */
301
302 /* following defines should be used for structure members */
303 #define __IM volatile const /*! Defines 'read only' structure member permissions */
304 #define __OM volatile /*! Defines 'write only' structure member permissions */
305 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
306
307 /*@} end of group Cortex_M35P */
308
309
310
311 /*******************************************************************************
312 * Register Abstraction
313 Core Register contain:
314 - Core Register
315 - Core NVIC Register
316 - Core SCB Register
317 - Core SysTick Register
318 - Core Debug Register
319 - Core MPU Register
320 - Core SAU Register
321 - Core FPU Register
322 ******************************************************************************/
323 /**
324 \defgroup CMSIS_core_register Defines and Type Definitions
325 \brief Type definitions and defines for Cortex-M processor based devices.
326 */
327
328 /**
329 \ingroup CMSIS_core_register
330 \defgroup CMSIS_CORE Status and Control Registers
331 \brief Core Register type definitions.
332 @{
333 */
334
335 /**
336 \brief Union type to access the Application Program Status Register (APSR).
337 */
338 typedef union
339 {
340 struct
341 {
342 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
343 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
344 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
345 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
346 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
347 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
348 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
349 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
350 } b; /*!< Structure used for bit access */
351 uint32_t w; /*!< Type used for word access */
352 } APSR_Type;
353
354 /** \brief APSR Register Definitions */
355 #define APSR_N_Pos 31U /*!< APSR: N Position */
356 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
357
358 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
359 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
360
361 #define APSR_C_Pos 29U /*!< APSR: C Position */
362 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
363
364 #define APSR_V_Pos 28U /*!< APSR: V Position */
365 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
366
367 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
368 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
369
370 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
371 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
372
373
374 /**
375 \brief Union type to access the Interrupt Program Status Register (IPSR).
376 */
377 typedef union
378 {
379 struct
380 {
381 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
382 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
383 } b; /*!< Structure used for bit access */
384 uint32_t w; /*!< Type used for word access */
385 } IPSR_Type;
386
387 /** \brief IPSR Register Definitions */
388 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
389 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
390
391
392 /**
393 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
394 */
395 typedef union
396 {
397 struct
398 {
399 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
400 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
401 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
402 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
403 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
404 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
405 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
406 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
407 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
408 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
409 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
410 } b; /*!< Structure used for bit access */
411 uint32_t w; /*!< Type used for word access */
412 } xPSR_Type;
413
414 /** \brief xPSR Register Definitions */
415 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
416 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
417
418 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
419 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
420
421 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
422 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
423
424 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
425 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
426
427 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
428 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
429
430 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
431 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
432
433 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
434 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
435
436 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
437 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
438
439 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
440 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
441
442
443 /**
444 \brief Union type to access the Control Registers (CONTROL).
445 */
446 typedef union
447 {
448 struct
449 {
450 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
451 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
452 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
453 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
454 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
455 } b; /*!< Structure used for bit access */
456 uint32_t w; /*!< Type used for word access */
457 } CONTROL_Type;
458
459 /** \brief CONTROL Register Definitions */
460 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
461 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
462
463 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
464 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
465
466 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
467 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
468
469 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
470 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
471
472 /*@} end of group CMSIS_CORE */
473
474
475 /**
476 \ingroup CMSIS_core_register
477 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
478 \brief Type definitions for the NVIC Registers
479 @{
480 */
481
482 /**
483 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
484 */
485 typedef struct
486 {
487 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
488 uint32_t RESERVED0[16U];
489 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
490 uint32_t RESERVED1[16U];
491 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
492 uint32_t RESERVED2[16U];
493 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
494 uint32_t RESERVED3[16U];
495 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
496 uint32_t RESERVED4[16U];
497 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
498 uint32_t RESERVED5[16U];
499 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
500 uint32_t RESERVED6[580U];
501 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
502 } NVIC_Type;
503
504 /** \brief NVIC Software Triggered Interrupt Register Definitions */
505 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
506 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
507
508 /*@} end of group CMSIS_NVIC */
509
510
511 /**
512 \ingroup CMSIS_core_register
513 \defgroup CMSIS_SCB System Control Block (SCB)
514 \brief Type definitions for the System Control Block Registers
515 @{
516 */
517
518 /**
519 \brief Structure type to access the System Control Block (SCB).
520 */
521 typedef struct
522 {
523 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
524 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
525 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
526 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
527 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
528 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
529 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
530 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
531 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
532 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
533 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
534 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
535 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
536 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
537 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
538 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
539 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
540 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
541 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
542 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
543 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
544 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
545 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
546 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
547 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
548 uint32_t RESERVED7[21U];
549 __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
550 __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
551 uint32_t RESERVED3[69U];
552 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
553 uint32_t RESERVED4[15U];
554 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
555 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
556 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
557 uint32_t RESERVED5[1U];
558 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
559 uint32_t RESERVED6[1U];
560 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
561 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
562 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
563 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
564 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
565 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
566 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
567 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
568 __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */
569 } SCB_Type;
570
571 /** \brief SCB CPUID Register Definitions */
572 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
573 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
574
575 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
576 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
577
578 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
579 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
580
581 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
582 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
583
584 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
585 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
586
587 /** \brief SCB Interrupt Control State Register Definitions */
588 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
589 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
590
591 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
592 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
593
594 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
595 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
596
597 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
598 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
599
600 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
601 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
602
603 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
604 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
605
606 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
607 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
608
609 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
610 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
611
612 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
613 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
614
615 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
616 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
617
618 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
619 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
620
621 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
622 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
623
624 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
625 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
626
627 /** \brief SCB Vector Table Offset Register Definitions */
628 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
629 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
630
631 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
632 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
633 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
634
635 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
636 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
637
638 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
639 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
640
641 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
642 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
643
644 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
645 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
646
647 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
648 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
649
650 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
651 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
652
653 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
654 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
655
656 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
657 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
658
659 /** \brief SCB System Control Register Definitions */
660 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
661 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
662
663 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
664 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
665
666 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
667 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
668
669 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
670 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
671
672 /** \brief SCB Configuration Control Register Definitions */
673 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
674 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
675
676 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
677 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
678
679 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
680 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
681
682 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
683 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
684
685 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
686 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
687
688 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
689 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
690
691 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
692 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
693
694 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
695 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
696
697 /** \brief SCB System Handler Control and State Register Definitions */
698 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
699 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
700
701 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
702 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
703
704 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
705 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
706
707 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
708 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
709
710 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
711 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
712
713 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
714 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
715
716 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
717 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
718
719 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
720 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
721
722 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
723 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
724
725 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
726 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
727
728 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
729 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
730
731 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
732 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
733
734 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
735 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
736
737 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
738 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
739
740 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
741 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
742
743 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
744 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
745
746 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
747 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
748
749 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
750 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
751
752 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
753 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
754
755 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
756 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
757
758 /** \brief SCB Configurable Fault Status Register Definitions */
759 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
760 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
761
762 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
763 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
764
765 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
766 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
767
768 /** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */
769 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
770 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
771
772 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
773 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
774
775 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
776 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
777
778 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
779 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
780
781 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
782 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
783
784 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
785 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
786
787 /** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
788 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
789 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
790
791 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
792 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
793
794 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
795 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
796
797 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
798 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
799
800 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
801 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
802
803 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
804 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
805
806 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
807 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
808
809 /** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
810 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
811 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
812
813 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
814 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
815
816 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
817 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
818
819 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
820 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
821
822 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
823 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
824
825 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
826 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
827
828 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
829 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
830
831 /** \brief SCB Hard Fault Status Register Definitions */
832 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
833 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
834
835 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
836 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
837
838 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
839 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
840
841 /** \brief SCB Debug Fault Status Register Definitions */
842 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
843 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
844
845 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
846 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
847
848 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
849 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
850
851 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
852 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
853
854 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
855 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
856
857 /** \brief SCB Non-Secure Access Control Register Definitions */
858 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
859 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
860
861 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
862 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
863
864 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
865 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
866
867 /** \brief SCB Cache Level ID Register Definitions */
868 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
869 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
870
871 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
872 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
873
874 /** \brief SCB Cache Type Register Definitions */
875 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
876 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
877
878 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
879 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
880
881 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
882 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
883
884 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
885 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
886
887 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
888 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
889
890 /** \brief SCB Cache Size ID Register Definitions */
891 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
892 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
893
894 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
895 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
896
897 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
898 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
899
900 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
901 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
902
903 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
904 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
905
906 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
907 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
908
909 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
910 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
911
912 /** \brief SCB Cache Size Selection Register Definitions */
913 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
914 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
915
916 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
917 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
918
919 /** \brief SCB Software Triggered Interrupt Register Definitions */
920 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
921 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
922
923 /** \brief SCB D-Cache Invalidate by Set-way Register Definitions */
924 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
925 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
926
927 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
928 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
929
930 /** \brief SCB D-Cache Clean by Set-way Register Definitions */
931 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
932 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
933
934 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
935 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
936
937 /** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
938 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
939 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
940
941 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
942 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
943
944 /*@} end of group CMSIS_SCB */
945
946
947 /**
948 \ingroup CMSIS_core_register
949 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
950 \brief Type definitions for the System Control and ID Register not in the SCB
951 @{
952 */
953
954 /**
955 \brief Structure type to access the System Control and ID Register not in the SCB.
956 */
957 typedef struct
958 {
959 uint32_t RESERVED0[1U];
960 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
961 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
962 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
963 } SCnSCB_Type;
964
965 /** \brief SCnSCB Interrupt Controller Type Register Definitions */
966 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
967 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
968
969 /*@} end of group CMSIS_SCnotSCB */
970
971
972 /**
973 \ingroup CMSIS_core_register
974 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
975 \brief Type definitions for the System Timer Registers.
976 @{
977 */
978
979 /**
980 \brief Structure type to access the System Timer (SysTick).
981 */
982 typedef struct
983 {
984 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
985 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
986 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
987 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
988 } SysTick_Type;
989
990 /** \brief SysTick Control / Status Register Definitions */
991 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
992 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
993
994 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
995 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
996
997 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
998 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
999
1000 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1001 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1002
1003 /** \brief SysTick Reload Register Definitions */
1004 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1005 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1006
1007 /** \brief SysTick Current Register Definitions */
1008 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1009 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1010
1011 /** \brief SysTick Calibration Register Definitions */
1012 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1013 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1014
1015 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1016 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1017
1018 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1019 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1020
1021 /*@} end of group CMSIS_SysTick */
1022
1023
1024 /**
1025 \ingroup CMSIS_core_register
1026 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1027 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1028 @{
1029 */
1030
1031 /**
1032 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1033 */
1034 typedef struct
1035 {
1036 __OM union
1037 {
1038 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
1039 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
1040 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
1041 } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */
1042 uint32_t RESERVED0[864U];
1043 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */
1044 uint32_t RESERVED1[15U];
1045 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */
1046 uint32_t RESERVED2[15U];
1047 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */
1048 uint32_t RESERVED3[27U];
1049 __IM uint32_t ITREAD; /*!< Offset: 0xEF0 (R/ ) Integration Read Register */
1050 uint32_t RESERVED4[1U];
1051 __OM uint32_t ITWRITE; /*!< Offset: 0xEF8 ( /W) Integration Write Register */
1052 uint32_t RESERVED5[1U];
1053 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */
1054 uint32_t RESERVED6[46U];
1055 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1056 uint32_t RESERVED7[3U];
1057 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
1058 } ITM_Type;
1059
1060 /** \brief ITM Stimulus Port Register Definitions */
1061 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1062 #define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1063
1064 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1065 #define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1066
1067 /** \brief ITM Trace Privilege Register Definitions */
1068 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1069 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1070
1071 /** \brief ITM Trace Control Register Definitions */
1072 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1073 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1074
1075 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1076 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1077
1078 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1079 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1080
1081 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1082 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1083
1084 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1085 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1086
1087 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1088 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1089
1090 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1091 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1092
1093 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1094 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1095
1096 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1097 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1098
1099 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1100 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1101
1102 /** \brief ITM Integration Read Register Definitions */
1103 #define ITM_ITREAD_AFVALID_Pos 1U /*!< ITM ITREAD: AFVALID Position */
1104 #define ITM_ITREAD_AFVALID_Msk (1UL << ITM_ITREAD_AFVALID_Pos) /*!< ITM ITREAD: AFVALID Mask */
1105
1106 #define ITM_ITREAD_ATREADY_Pos 0U /*!< ITM ITREAD: ATREADY Position */
1107 #define ITM_ITREAD_ATREADY_Msk (1UL /*<< ITM_ITREAD_ATREADY_Pos*/) /*!< ITM ITREAD: ATREADY Mask */
1108
1109 /** \brief ITM Integration Write Register Definitions */
1110 #define ITM_ITWRITE_AFVALID_Pos 1U /*!< ITM ITWRITE: AFVALID Position */
1111 #define ITM_ITWRITE_AFVALID_Msk (1UL << ITM_ITWRITE_AFVALID_Pos) /*!< ITM ITWRITE: AFVALID Mask */
1112
1113 #define ITM_ITWRITE_ATREADY_Pos 0U /*!< ITM ITWRITE: ATREADY Position */
1114 #define ITM_ITWRITE_ATREADY_Msk (1UL /*<< ITM_ITWRITE_ATREADY_Pos*/) /*!< ITM ITWRITE: ATREADY Mask */
1115
1116 /** \brief ITM Integration Mode Control Register Definitions */
1117 #define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */
1118 #define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */
1119
1120 /*@}*/ /* end of group CMSIS_ITM */
1121
1122
1123 /**
1124 \ingroup CMSIS_core_register
1125 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1126 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1127 @{
1128 */
1129
1130 /**
1131 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1132 */
1133 typedef struct
1134 {
1135 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1136 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1137 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1138 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1139 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1140 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1141 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1142 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1143 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1144 uint32_t RESERVED1[1U];
1145 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1146 uint32_t RESERVED2[1U];
1147 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1148 uint32_t RESERVED3[1U];
1149 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1150 uint32_t RESERVED4[1U];
1151 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1152 uint32_t RESERVED5[1U];
1153 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1154 uint32_t RESERVED6[1U];
1155 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1156 uint32_t RESERVED7[1U];
1157 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1158 uint32_t RESERVED14[984U];
1159 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */
1160 uint32_t RESERVED15[3U];
1161 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1162 } DWT_Type;
1163
1164 /** \brief DWT Control Register Definitions */
1165 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1166 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1167
1168 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1169 #define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1170
1171 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1172 #define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1173
1174 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1175 #define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1176
1177 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1178 #define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1179
1180 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1181 #define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1182
1183 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1184 #define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1185
1186 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1187 #define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1188
1189 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1190 #define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1191
1192 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1193 #define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1194
1195 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1196 #define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1197
1198 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1199 #define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1200
1201 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1202 #define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1203
1204 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1205 #define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1206
1207 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1208 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1209
1210 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1211 #define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1212
1213 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1214 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1215
1216 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1217 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1218
1219 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1220 #define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1221
1222 /** \brief DWT CPI Count Register Definitions */
1223 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1224 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1225
1226 /** \brief DWT Exception Overhead Count Register Definitions */
1227 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1228 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1229
1230 /** \brief DWT Sleep Count Register Definitions */
1231 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1232 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1233
1234 /** \brief DWT LSU Count Register Definitions */
1235 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1236 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1237
1238 /** \brief DWT Folded-instruction Count Register Definitions */
1239 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1240 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1241
1242 /** \brief DWT Comparator Function Register Definitions */
1243 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1244 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1245
1246 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1247 #define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1248
1249 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1250 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1251
1252 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1253 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1254
1255 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1256 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1257
1258 /*@}*/ /* end of group CMSIS_DWT */
1259
1260
1261 /**
1262 \ingroup CMSIS_core_register
1263 \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU)
1264 \brief Type definitions for the Trace Port Interface Unit (TPIU)
1265 @{
1266 */
1267
1268 /**
1269 \brief Structure type to access the Trace Port Interface Unit Register (TPIU).
1270 */
1271 typedef struct
1272 {
1273 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1274 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1275 uint32_t RESERVED0[2U];
1276 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1277 uint32_t RESERVED1[55U];
1278 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1279 uint32_t RESERVED2[131U];
1280 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1281 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1282 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
1283 uint32_t RESERVED3[759U];
1284 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1285 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
1286 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
1287 uint32_t RESERVED4[1U];
1288 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
1289 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
1290 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1291 uint32_t RESERVED5[39U];
1292 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1293 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1294 uint32_t RESERVED7[8U];
1295 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
1296 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1297 } TPIU_Type;
1298
1299 /** \brief TPIU Asynchronous Clock Prescaler Register Definitions */
1300 #define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */
1301 #define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */
1302
1303 /** \brief TPIU Selected Pin Protocol Register Definitions */
1304 #define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */
1305 #define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */
1306
1307 /** \brief TPIU Formatter and Flush Status Register Definitions */
1308 #define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */
1309 #define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */
1310
1311 #define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */
1312 #define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */
1313
1314 #define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */
1315 #define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */
1316
1317 #define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */
1318 #define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */
1319
1320 /** \brief TPIU Formatter and Flush Control Register Definitions */
1321 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */
1322 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */
1323
1324 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */
1325 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */
1326
1327 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */
1328 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
1329
1330 /** \brief TPIU Periodic Synchronization Control Register Definitions */
1331 #define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */
1332 #define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */
1333
1334 /** \brief TPIU TRIGGER Register Definitions */
1335 #define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */
1336 #define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */
1337
1338 /** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */
1339 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */
1340 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */
1341
1342 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */
1343 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */
1344
1345 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */
1346 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */
1347
1348 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */
1349 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */
1350
1351 #define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */
1352 #define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */
1353
1354 #define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */
1355 #define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */
1356
1357 #define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */
1358 #define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */
1359
1360 /** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */
1361 #define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */
1362 #define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */
1363
1364 #define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */
1365 #define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */
1366
1367 #define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */
1368 #define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */
1369
1370 #define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */
1371 #define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */
1372
1373 /** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */
1374 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */
1375 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */
1376
1377 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */
1378 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */
1379
1380 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */
1381 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */
1382
1383 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */
1384 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */
1385
1386 #define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */
1387 #define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */
1388
1389 #define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */
1390 #define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */
1391
1392 #define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */
1393 #define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */
1394
1395 /** \brief TPIU Integration Test ATB Control Register 0 Definitions */
1396 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */
1397 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */
1398
1399 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */
1400 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */
1401
1402 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */
1403 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */
1404
1405 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */
1406 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
1407
1408 /** \brief TPIU Integration Mode Control Register Definitions */
1409 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */
1410 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
1411
1412 /** \brief TPIU DEVID Register Definitions */
1413 #define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */
1414 #define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */
1415
1416 #define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */
1417 #define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */
1418
1419 #define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */
1420 #define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */
1421
1422 #define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */
1423 #define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */
1424
1425 #define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */
1426 #define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */
1427
1428 /** \brief TPIU DEVTYPE Register Definitions */
1429 #define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */
1430 #define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */
1431
1432 #define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */
1433 #define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
1434
1435 /*@}*/ /* end of group CMSIS_TPIU */
1436
1437
1438 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1439 /**
1440 \ingroup CMSIS_core_register
1441 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1442 \brief Type definitions for the Memory Protection Unit (MPU)
1443 @{
1444 */
1445
1446 /**
1447 \brief Structure type to access the Memory Protection Unit (MPU).
1448 */
1449 typedef struct
1450 {
1451 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1452 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1453 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1454 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1455 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1456 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1457 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1458 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1459 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1460 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1461 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1462 uint32_t RESERVED0[1];
1463 union {
1464 __IOM uint32_t MAIR[2];
1465 struct {
1466 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1467 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1468 };
1469 };
1470 } MPU_Type;
1471
1472 #define MPU_TYPE_RALIASES 4U
1473
1474 /** \brief MPU Type Register Definitions */
1475 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1476 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1477
1478 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1479 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1480
1481 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1482 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1483
1484 /** \brief MPU Control Register Definitions */
1485 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1486 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1487
1488 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1489 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1490
1491 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1492 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1493
1494 /** \brief MPU Region Number Register Definitions */
1495 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1496 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1497
1498 /** \brief MPU Region Base Address Register Definitions */
1499 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
1500 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
1501
1502 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1503 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1504
1505 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1506 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1507
1508 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1509 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1510
1511 /** \brief MPU Region Limit Address Register Definitions */
1512 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1513 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1514
1515 #define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */
1516 #define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */
1517
1518 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1519 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1520
1521 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1522 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */
1523
1524 /** \brief MPU Memory Attribute Indirection Register 0 Definitions */
1525 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1526 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1527
1528 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1529 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1530
1531 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1532 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1533
1534 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1535 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1536
1537 /** \brief MPU Memory Attribute Indirection Register 1 Definitions */
1538 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1539 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1540
1541 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1542 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1543
1544 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1545 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1546
1547 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1548 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1549
1550 /*@} end of group CMSIS_MPU */
1551 #endif
1552
1553
1554 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1555 /**
1556 \ingroup CMSIS_core_register
1557 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1558 \brief Type definitions for the Security Attribution Unit (SAU)
1559 @{
1560 */
1561
1562 /**
1563 \brief Structure type to access the Security Attribution Unit (SAU).
1564 */
1565 typedef struct
1566 {
1567 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1568 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1569 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1570 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1571 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1572 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1573 #else
1574 uint32_t RESERVED0[3];
1575 #endif
1576 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1577 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1578 } SAU_Type;
1579
1580 /** \brief SAU Control Register Definitions */
1581 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1582 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1583
1584 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1585 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1586
1587 /** \brief SAU Type Register Definitions */
1588 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1589 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1590
1591 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1592 /** \brief SAU Region Number Register Definitions */
1593 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1594 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1595
1596 /** \brief SAU Region Base Address Register Definitions */
1597 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1598 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1599
1600 /** \brief SAU Region Limit Address Register Definitions */
1601 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1602 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1603
1604 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1605 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1606
1607 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1608 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1609
1610 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1611
1612 /** \brief SAU Secure Fault Status Register Definitions */
1613 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1614 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1615
1616 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1617 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1618
1619 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1620 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1621
1622 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1623 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1624
1625 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1626 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1627
1628 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1629 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1630
1631 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1632 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1633
1634 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1635 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1636
1637 /*@} end of group CMSIS_SAU */
1638 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1639
1640
1641 /**
1642 \ingroup CMSIS_core_register
1643 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1644 \brief Type definitions for the Floating Point Unit (FPU)
1645 @{
1646 */
1647
1648 /**
1649 \brief Structure type to access the Floating Point Unit (FPU).
1650 */
1651 typedef struct
1652 {
1653 uint32_t RESERVED0[1U];
1654 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1655 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1656 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1657 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
1658 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
1659 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
1660 } FPU_Type;
1661
1662 /** \brief FPU Floating-Point Context Control Register Definitions */
1663 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1664 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1665
1666 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1667 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1668
1669 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1670 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1671
1672 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1673 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1674
1675 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1676 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1677
1678 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1679 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1680
1681 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1682 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1683
1684 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1685 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1686
1687 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1688 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1689
1690 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1691 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1692
1693 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1694 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1695
1696 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1697 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1698
1699 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1700 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1701
1702 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1703 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1704
1705 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1706 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1707
1708 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1709 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1710
1711 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1712 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1713
1714 /** \brief FPU Floating-Point Context Address Register Definitions */
1715 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1716 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1717
1718 /** \brief FPU Floating-Point Default Status Control Register Definitions */
1719 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1720 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1721
1722 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1723 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1724
1725 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1726 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1727
1728 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1729 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1730
1731 /** \brief FPU Media and VFP Feature Register 0 Definitions */
1732 #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */
1733 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */
1734
1735 #define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */
1736 #define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */
1737
1738 #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */
1739 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */
1740
1741 #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */
1742 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
1743
1744 #define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */
1745 #define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */
1746
1747 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */
1748 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
1749
1750 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */
1751 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
1752
1753 #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */
1754 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */
1755
1756 /** \brief FPU Media and VFP Feature Register 1 Definitions */
1757 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */
1758 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */
1759
1760 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1761 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1762
1763 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1764 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1765
1766 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1767 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1768
1769 /** \brief FPU Media and VFP Feature Register 2 Definitions */
1770 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1771 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1772
1773 /*@} end of group CMSIS_FPU */
1774
1775
1776 /**
1777 \ingroup CMSIS_core_register
1778 \defgroup CMSIS_DCB Debug Control Block
1779 \brief Type definitions for the Debug Control Block Registers
1780 @{
1781 */
1782
1783 /**
1784 \brief Structure type to access the Debug Control Block Registers (DCB).
1785 */
1786 typedef struct
1787 {
1788 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1789 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1790 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1791 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1792 uint32_t RESERVED0[1U];
1793 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1794 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1795 } DCB_Type;
1796
1797 /** \brief DCB Debug Halting Control and Status Register Definitions */
1798 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1799 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1800
1801 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1802 #define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1803
1804 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1805 #define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1806
1807 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1808 #define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1809
1810 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1811 #define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1812
1813 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1814 #define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1815
1816 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1817 #define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1818
1819 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1820 #define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1821
1822 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1823 #define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1824
1825 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1826 #define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1827
1828 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1829 #define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1830
1831 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1832 #define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1833
1834 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1835 #define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1836
1837 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1838 #define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1839
1840 /** \brief DCB Debug Core Register Selector Register Definitions */
1841 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1842 #define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1843
1844 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1845 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1846
1847 /** \brief DCB Debug Core Register Data Register Definitions */
1848 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1849 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1850
1851 /** \brief DCB Debug Exception and Monitor Control Register Definitions */
1852 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1853 #define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1854
1855 #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
1856 #define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
1857
1858 #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
1859 #define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
1860
1861 #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
1862 #define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
1863
1864 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
1865 #define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
1866
1867 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
1868 #define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
1869
1870 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
1871 #define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
1872
1873 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
1874 #define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
1875
1876 #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
1877 #define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
1878
1879 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1880 #define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1881
1882 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
1883 #define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
1884
1885 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
1886 #define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
1887
1888 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
1889 #define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
1890
1891 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
1892 #define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
1893
1894 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
1895 #define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
1896
1897 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
1898 #define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
1899
1900 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1901 #define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1902
1903 /** \brief DCB Debug Authentication Control Register Definitions */
1904 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
1905 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
1906
1907 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
1908 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
1909
1910 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
1911 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
1912
1913 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
1914 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
1915
1916 /** \brief DCB Debug Security Control and Status Register Definitions */
1917 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
1918 #define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
1919
1920 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
1921 #define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
1922
1923 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
1924 #define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
1925
1926 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
1927 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
1928
1929 /*@} end of group CMSIS_DCB */
1930
1931
1932 /**
1933 \ingroup CMSIS_core_register
1934 \defgroup CMSIS_DIB Debug Identification Block
1935 \brief Type definitions for the Debug Identification Block Registers
1936 @{
1937 */
1938
1939 /**
1940 \brief Structure type to access the Debug Identification Block Registers (DIB).
1941 */
1942 typedef struct
1943 {
1944 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
1945 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
1946 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
1947 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
1948 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
1949 } DIB_Type;
1950
1951 /** \brief DIB SCS Software Lock Access Register Definitions */
1952 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
1953 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
1954
1955 /** \brief DIB SCS Software Lock Status Register Definitions */
1956 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
1957 #define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
1958
1959 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
1960 #define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
1961
1962 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
1963 #define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
1964
1965 /** \brief DIB Debug Authentication Status Register Definitions */
1966 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
1967 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
1968
1969 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
1970 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
1971
1972 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
1973 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
1974
1975 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
1976 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
1977
1978 /** \brief DIB SCS Device Architecture Register Definitions */
1979 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
1980 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
1981
1982 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
1983 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
1984
1985 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
1986 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
1987
1988 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
1989 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
1990
1991 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
1992 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
1993
1994 /** \brief DIB SCS Device Type Register Definitions */
1995 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
1996 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
1997
1998 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
1999 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
2000
2001 /*@} end of group CMSIS_DIB */
2002
2003
2004 /**
2005 \ingroup CMSIS_core_register
2006 \defgroup CMSIS_core_bitfield Core register bit field macros
2007 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
2008 @{
2009 */
2010
2011 /**
2012 \brief Mask and shift a bit field value for use in a register bit range.
2013 \param[in] field Name of the register bit field.
2014 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
2015 \return Masked and shifted value.
2016 */
2017 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2018
2019 /**
2020 \brief Mask and shift a register value to extract a bit filed value.
2021 \param[in] field Name of the register bit field.
2022 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
2023 \return Masked and shifted bit field value.
2024 */
2025 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2026
2027 /*@} end of group CMSIS_core_bitfield */
2028
2029
2030 /**
2031 \ingroup CMSIS_core_register
2032 \defgroup CMSIS_core_base Core Definitions
2033 \brief Definitions for base addresses, unions, and structures.
2034 @{
2035 */
2036
2037 /* Memory mapping of Core Hardware */
2038 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
2039 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
2040 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
2041 #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */
2042 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
2043 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
2044 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
2045 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
2046 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
2047
2048 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
2049 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
2050 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
2051 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
2052 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
2053 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
2054 #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
2055 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
2056 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
2057
2058 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2059 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
2060 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
2061 #endif
2062
2063 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2064 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2065 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2066 #endif
2067
2068 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2069 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2070
2071 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2072 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2073 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
2074 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
2075 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2076 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2077 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2078
2079 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2080 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2081 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2082 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2083 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
2084 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
2085
2086 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2087 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2088 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2089 #endif
2090
2091 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2092 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2093
2094 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2095 /*@} */
2096
2097
2098 /**
2099 \ingroup CMSIS_core_register
2100 \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
2101 \brief Register alias definitions for backwards compatibility.
2102 @{
2103 */
2104
2105 /*@} */
2106
2107
2108 /*******************************************************************************
2109 * Hardware Abstraction Layer
2110 Core Function Interface contains:
2111 - Core NVIC Functions
2112 - Core SysTick Functions
2113 - Core Debug Functions
2114 - Core Register Access Functions
2115 ******************************************************************************/
2116 /**
2117 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2118 */
2119
2120
2121
2122 /* ########################## NVIC functions #################################### */
2123 /**
2124 \ingroup CMSIS_Core_FunctionInterface
2125 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2126 \brief Functions that manage interrupts and exceptions via the NVIC.
2127 @{
2128 */
2129
2130 #ifdef CMSIS_NVIC_VIRTUAL
2131 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2132 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2133 #endif
2134 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2135 #else
2136 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2137 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2138 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2139 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2140 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2141 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2142 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2143 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2144 #define NVIC_GetActive __NVIC_GetActive
2145 #define NVIC_SetPriority __NVIC_SetPriority
2146 #define NVIC_GetPriority __NVIC_GetPriority
2147 #define NVIC_SystemReset __NVIC_SystemReset
2148 #endif /* CMSIS_NVIC_VIRTUAL */
2149
2150 #ifdef CMSIS_VECTAB_VIRTUAL
2151 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2152 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2153 #endif
2154 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2155 #else
2156 #define NVIC_SetVector __NVIC_SetVector
2157 #define NVIC_GetVector __NVIC_GetVector
2158 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2159
2160 #define NVIC_USER_IRQ_OFFSET 16
2161
2162
2163 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2164
2165 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2166 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2167
2168 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2169 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2170 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2171 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2172 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2173 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2174 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2175 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2176
2177 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2178 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2179 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2180 #else
2181 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2182 #endif
2183
2184
2185 /**
2186 \brief Set Priority Grouping
2187 \details Sets the priority grouping field using the required unlock sequence.
2188 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2189 Only values from 0..7 are used.
2190 In case of a conflict between priority grouping and available
2191 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2192 \param [in] PriorityGroup Priority grouping field.
2193 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)2194 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2195 {
2196 uint32_t reg_value;
2197 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2198
2199 reg_value = SCB->AIRCR; /* read old register configuration */
2200 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2201 reg_value = (reg_value |
2202 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2203 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2204 SCB->AIRCR = reg_value;
2205 }
2206
2207
2208 /**
2209 \brief Get Priority Grouping
2210 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2211 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2212 */
__NVIC_GetPriorityGrouping(void)2213 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2214 {
2215 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2216 }
2217
2218
2219 /**
2220 \brief Enable Interrupt
2221 \details Enables a device specific interrupt in the NVIC interrupt controller.
2222 \param [in] IRQn Device specific interrupt number.
2223 \note IRQn must not be negative.
2224 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2225 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2226 {
2227 if ((int32_t)(IRQn) >= 0)
2228 {
2229 __COMPILER_BARRIER();
2230 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2231 __COMPILER_BARRIER();
2232 }
2233 }
2234
2235
2236 /**
2237 \brief Get Interrupt Enable status
2238 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2239 \param [in] IRQn Device specific interrupt number.
2240 \return 0 Interrupt is not enabled.
2241 \return 1 Interrupt is enabled.
2242 \note IRQn must not be negative.
2243 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2244 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2245 {
2246 if ((int32_t)(IRQn) >= 0)
2247 {
2248 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2249 }
2250 else
2251 {
2252 return(0U);
2253 }
2254 }
2255
2256
2257 /**
2258 \brief Disable Interrupt
2259 \details Disables a device specific interrupt in the NVIC interrupt controller.
2260 \param [in] IRQn Device specific interrupt number.
2261 \note IRQn must not be negative.
2262 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2263 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2264 {
2265 if ((int32_t)(IRQn) >= 0)
2266 {
2267 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2268 __DSB();
2269 __ISB();
2270 }
2271 }
2272
2273
2274 /**
2275 \brief Get Pending Interrupt
2276 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2277 \param [in] IRQn Device specific interrupt number.
2278 \return 0 Interrupt status is not pending.
2279 \return 1 Interrupt status is pending.
2280 \note IRQn must not be negative.
2281 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2282 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2283 {
2284 if ((int32_t)(IRQn) >= 0)
2285 {
2286 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2287 }
2288 else
2289 {
2290 return(0U);
2291 }
2292 }
2293
2294
2295 /**
2296 \brief Set Pending Interrupt
2297 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2298 \param [in] IRQn Device specific interrupt number.
2299 \note IRQn must not be negative.
2300 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2301 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2302 {
2303 if ((int32_t)(IRQn) >= 0)
2304 {
2305 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2306 }
2307 }
2308
2309
2310 /**
2311 \brief Clear Pending Interrupt
2312 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2313 \param [in] IRQn Device specific interrupt number.
2314 \note IRQn must not be negative.
2315 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2316 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2317 {
2318 if ((int32_t)(IRQn) >= 0)
2319 {
2320 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2321 }
2322 }
2323
2324
2325 /**
2326 \brief Get Active Interrupt
2327 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2328 \param [in] IRQn Device specific interrupt number.
2329 \return 0 Interrupt status is not active.
2330 \return 1 Interrupt status is active.
2331 \note IRQn must not be negative.
2332 */
__NVIC_GetActive(IRQn_Type IRQn)2333 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2334 {
2335 if ((int32_t)(IRQn) >= 0)
2336 {
2337 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2338 }
2339 else
2340 {
2341 return(0U);
2342 }
2343 }
2344
2345
2346 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2347 /**
2348 \brief Get Interrupt Target State
2349 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2350 \param [in] IRQn Device specific interrupt number.
2351 \return 0 if interrupt is assigned to Secure
2352 \return 1 if interrupt is assigned to Non Secure
2353 \note IRQn must not be negative.
2354 */
NVIC_GetTargetState(IRQn_Type IRQn)2355 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2356 {
2357 if ((int32_t)(IRQn) >= 0)
2358 {
2359 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2360 }
2361 else
2362 {
2363 return(0U);
2364 }
2365 }
2366
2367
2368 /**
2369 \brief Set Interrupt Target State
2370 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2371 \param [in] IRQn Device specific interrupt number.
2372 \return 0 if interrupt is assigned to Secure
2373 1 if interrupt is assigned to Non Secure
2374 \note IRQn must not be negative.
2375 */
NVIC_SetTargetState(IRQn_Type IRQn)2376 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2377 {
2378 if ((int32_t)(IRQn) >= 0)
2379 {
2380 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2381 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2382 }
2383 else
2384 {
2385 return(0U);
2386 }
2387 }
2388
2389
2390 /**
2391 \brief Clear Interrupt Target State
2392 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2393 \param [in] IRQn Device specific interrupt number.
2394 \return 0 if interrupt is assigned to Secure
2395 1 if interrupt is assigned to Non Secure
2396 \note IRQn must not be negative.
2397 */
NVIC_ClearTargetState(IRQn_Type IRQn)2398 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2399 {
2400 if ((int32_t)(IRQn) >= 0)
2401 {
2402 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2403 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2404 }
2405 else
2406 {
2407 return(0U);
2408 }
2409 }
2410 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2411
2412
2413 /**
2414 \brief Set Interrupt Priority
2415 \details Sets the priority of a device specific interrupt or a processor exception.
2416 The interrupt number can be positive to specify a device specific interrupt,
2417 or negative to specify a processor exception.
2418 \param [in] IRQn Interrupt number.
2419 \param [in] priority Priority to set.
2420 \note The priority cannot be set for every processor exception.
2421 */
__NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)2422 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2423 {
2424 if ((int32_t)(IRQn) >= 0)
2425 {
2426 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2427 }
2428 else
2429 {
2430 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2431 }
2432 }
2433
2434
2435 /**
2436 \brief Get Interrupt Priority
2437 \details Reads the priority of a device specific interrupt or a processor exception.
2438 The interrupt number can be positive to specify a device specific interrupt,
2439 or negative to specify a processor exception.
2440 \param [in] IRQn Interrupt number.
2441 \return Interrupt Priority.
2442 Value is aligned automatically to the implemented priority bits of the microcontroller.
2443 */
__NVIC_GetPriority(IRQn_Type IRQn)2444 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2445 {
2446
2447 if ((int32_t)(IRQn) >= 0)
2448 {
2449 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2450 }
2451 else
2452 {
2453 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2454 }
2455 }
2456
2457
2458 /**
2459 \brief Encode Priority
2460 \details Encodes the priority for an interrupt with the given priority group,
2461 preemptive priority value, and subpriority value.
2462 In case of a conflict between priority grouping and available
2463 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2464 \param [in] PriorityGroup Used priority group.
2465 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2466 \param [in] SubPriority Subpriority value (starting from 0).
2467 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2468 */
NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)2469 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2470 {
2471 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2472 uint32_t PreemptPriorityBits;
2473 uint32_t SubPriorityBits;
2474
2475 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2476 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2477
2478 return (
2479 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2480 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2481 );
2482 }
2483
2484
2485 /**
2486 \brief Decode Priority
2487 \details Decodes an interrupt priority value with a given priority group to
2488 preemptive priority value and subpriority value.
2489 In case of a conflict between priority grouping and available
2490 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2491 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2492 \param [in] PriorityGroup Used priority group.
2493 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2494 \param [out] pSubPriority Subpriority value (starting from 0).
2495 */
NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)2496 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2497 {
2498 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2499 uint32_t PreemptPriorityBits;
2500 uint32_t SubPriorityBits;
2501
2502 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2503 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2504
2505 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2506 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2507 }
2508
2509
2510 /**
2511 \brief Set Interrupt Vector
2512 \details Sets an interrupt vector in SRAM based interrupt vector table.
2513 The interrupt number can be positive to specify a device specific interrupt,
2514 or negative to specify a processor exception.
2515 VTOR must been relocated to SRAM before.
2516 \param [in] IRQn Interrupt number
2517 \param [in] vector Address of interrupt handler function
2518 */
__NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)2519 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2520 {
2521 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
2522 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2523 __DSB();
2524 }
2525
2526
2527 /**
2528 \brief Get Interrupt Vector
2529 \details Reads an interrupt vector from interrupt vector table.
2530 The interrupt number can be positive to specify a device specific interrupt,
2531 or negative to specify a processor exception.
2532 \param [in] IRQn Interrupt number.
2533 \return Address of interrupt handler function
2534 */
__NVIC_GetVector(IRQn_Type IRQn)2535 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2536 {
2537 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
2538 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2539 }
2540
2541
2542 /**
2543 \brief System Reset
2544 \details Initiates a system reset request to reset the MCU.
2545 */
__NVIC_SystemReset(void)2546 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2547 {
2548 __DSB(); /* Ensure all outstanding memory accesses included
2549 buffered write are completed before reset */
2550 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2551 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2552 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2553 __DSB(); /* Ensure completion of memory access */
2554
2555 for(;;) /* wait until reset */
2556 {
2557 __NOP();
2558 }
2559 }
2560
2561 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2562 /**
2563 \brief Set Priority Grouping (non-secure)
2564 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2565 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2566 Only values from 0..7 are used.
2567 In case of a conflict between priority grouping and available
2568 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2569 \param [in] PriorityGroup Priority grouping field.
2570 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)2571 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2572 {
2573 uint32_t reg_value;
2574 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2575
2576 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2577 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2578 reg_value = (reg_value |
2579 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2580 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2581 SCB_NS->AIRCR = reg_value;
2582 }
2583
2584
2585 /**
2586 \brief Get Priority Grouping (non-secure)
2587 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2588 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2589 */
TZ_NVIC_GetPriorityGrouping_NS(void)2590 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2591 {
2592 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2593 }
2594
2595
2596 /**
2597 \brief Enable Interrupt (non-secure)
2598 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2599 \param [in] IRQn Device specific interrupt number.
2600 \note IRQn must not be negative.
2601 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)2602 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2603 {
2604 if ((int32_t)(IRQn) >= 0)
2605 {
2606 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2607 }
2608 }
2609
2610
2611 /**
2612 \brief Get Interrupt Enable status (non-secure)
2613 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2614 \param [in] IRQn Device specific interrupt number.
2615 \return 0 Interrupt is not enabled.
2616 \return 1 Interrupt is enabled.
2617 \note IRQn must not be negative.
2618 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)2619 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2620 {
2621 if ((int32_t)(IRQn) >= 0)
2622 {
2623 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2624 }
2625 else
2626 {
2627 return(0U);
2628 }
2629 }
2630
2631
2632 /**
2633 \brief Disable Interrupt (non-secure)
2634 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2635 \param [in] IRQn Device specific interrupt number.
2636 \note IRQn must not be negative.
2637 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)2638 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2639 {
2640 if ((int32_t)(IRQn) >= 0)
2641 {
2642 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2643 }
2644 }
2645
2646
2647 /**
2648 \brief Get Pending Interrupt (non-secure)
2649 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2650 \param [in] IRQn Device specific interrupt number.
2651 \return 0 Interrupt status is not pending.
2652 \return 1 Interrupt status is pending.
2653 \note IRQn must not be negative.
2654 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)2655 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2656 {
2657 if ((int32_t)(IRQn) >= 0)
2658 {
2659 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2660 }
2661 else
2662 {
2663 return(0U);
2664 }
2665 }
2666
2667
2668 /**
2669 \brief Set Pending Interrupt (non-secure)
2670 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2671 \param [in] IRQn Device specific interrupt number.
2672 \note IRQn must not be negative.
2673 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)2674 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2675 {
2676 if ((int32_t)(IRQn) >= 0)
2677 {
2678 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2679 }
2680 }
2681
2682
2683 /**
2684 \brief Clear Pending Interrupt (non-secure)
2685 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2686 \param [in] IRQn Device specific interrupt number.
2687 \note IRQn must not be negative.
2688 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)2689 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2690 {
2691 if ((int32_t)(IRQn) >= 0)
2692 {
2693 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2694 }
2695 }
2696
2697
2698 /**
2699 \brief Get Active Interrupt (non-secure)
2700 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2701 \param [in] IRQn Device specific interrupt number.
2702 \return 0 Interrupt status is not active.
2703 \return 1 Interrupt status is active.
2704 \note IRQn must not be negative.
2705 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)2706 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2707 {
2708 if ((int32_t)(IRQn) >= 0)
2709 {
2710 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2711 }
2712 else
2713 {
2714 return(0U);
2715 }
2716 }
2717
2718
2719 /**
2720 \brief Set Interrupt Priority (non-secure)
2721 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2722 The interrupt number can be positive to specify a device specific interrupt,
2723 or negative to specify a processor exception.
2724 \param [in] IRQn Interrupt number.
2725 \param [in] priority Priority to set.
2726 \note The priority cannot be set for every non-secure processor exception.
2727 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)2728 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2729 {
2730 if ((int32_t)(IRQn) >= 0)
2731 {
2732 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2733 }
2734 else
2735 {
2736 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2737 }
2738 }
2739
2740
2741 /**
2742 \brief Get Interrupt Priority (non-secure)
2743 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2744 The interrupt number can be positive to specify a device specific interrupt,
2745 or negative to specify a processor exception.
2746 \param [in] IRQn Interrupt number.
2747 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2748 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2749 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2750 {
2751
2752 if ((int32_t)(IRQn) >= 0)
2753 {
2754 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2755 }
2756 else
2757 {
2758 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2759 }
2760 }
2761 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2762
2763 /*@} end of CMSIS_Core_NVICFunctions */
2764
2765 /* ########################## MPU functions #################################### */
2766
2767 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2768
2769 #include "m-profile/armv8m_mpu.h"
2770
2771 #endif
2772
2773
2774 /* ########################## FPU functions #################################### */
2775 /**
2776 \ingroup CMSIS_Core_FunctionInterface
2777 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2778 \brief Function that provides FPU type.
2779 @{
2780 */
2781
2782 /**
2783 \brief get FPU type
2784 \details returns the FPU type
2785 \returns
2786 - \b 0: No FPU
2787 - \b 1: Single precision FPU
2788 - \b 2: Double + Single precision FPU
2789 */
SCB_GetFPUType(void)2790 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2791 {
2792 uint32_t mvfr0;
2793
2794 mvfr0 = FPU->MVFR0;
2795 if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
2796 {
2797 return 2U; /* Double + Single precision FPU */
2798 }
2799 else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
2800 {
2801 return 1U; /* Single precision FPU */
2802 }
2803 else
2804 {
2805 return 0U; /* No FPU */
2806 }
2807 }
2808
2809 /*@} end of CMSIS_Core_FpuFunctions */
2810
2811
2812
2813 /* ########################## SAU functions #################################### */
2814 /**
2815 \ingroup CMSIS_Core_FunctionInterface
2816 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2817 \brief Functions that configure the SAU.
2818 @{
2819 */
2820
2821 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2822
2823 /**
2824 \brief Enable SAU
2825 \details Enables the Security Attribution Unit (SAU).
2826 */
TZ_SAU_Enable(void)2827 __STATIC_INLINE void TZ_SAU_Enable(void)
2828 {
2829 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2830 }
2831
2832
2833
2834 /**
2835 \brief Disable SAU
2836 \details Disables the Security Attribution Unit (SAU).
2837 */
TZ_SAU_Disable(void)2838 __STATIC_INLINE void TZ_SAU_Disable(void)
2839 {
2840 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2841 }
2842
2843 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2844
2845 /*@} end of CMSIS_Core_SAUFunctions */
2846
2847
2848
2849
2850 /* ################################## Debug Control function ############################################ */
2851 /**
2852 \ingroup CMSIS_Core_FunctionInterface
2853 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
2854 \brief Functions that access the Debug Control Block.
2855 @{
2856 */
2857
2858
2859 /**
2860 \brief Set Debug Authentication Control Register
2861 \details writes to Debug Authentication Control register.
2862 \param [in] value value to be writen.
2863 */
DCB_SetAuthCtrl(uint32_t value)2864 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2865 {
2866 __DSB();
2867 __ISB();
2868 DCB->DAUTHCTRL = value;
2869 __DSB();
2870 __ISB();
2871 }
2872
2873
2874 /**
2875 \brief Get Debug Authentication Control Register
2876 \details Reads Debug Authentication Control register.
2877 \return Debug Authentication Control Register.
2878 */
DCB_GetAuthCtrl(void)2879 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2880 {
2881 return (DCB->DAUTHCTRL);
2882 }
2883
2884
2885 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2886 /**
2887 \brief Set Debug Authentication Control Register (non-secure)
2888 \details writes to non-secure Debug Authentication Control register when in secure state.
2889 \param [in] value value to be writen
2890 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)2891 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
2892 {
2893 __DSB();
2894 __ISB();
2895 DCB_NS->DAUTHCTRL = value;
2896 __DSB();
2897 __ISB();
2898 }
2899
2900
2901 /**
2902 \brief Get Debug Authentication Control Register (non-secure)
2903 \details Reads non-secure Debug Authentication Control register when in secure state.
2904 \return Debug Authentication Control Register.
2905 */
TZ_DCB_GetAuthCtrl_NS(void)2906 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
2907 {
2908 return (DCB_NS->DAUTHCTRL);
2909 }
2910 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2911
2912 /*@} end of CMSIS_Core_DCBFunctions */
2913
2914
2915
2916
2917 /* ################################## Debug Identification function ############################################ */
2918 /**
2919 \ingroup CMSIS_Core_FunctionInterface
2920 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
2921 \brief Functions that access the Debug Identification Block.
2922 @{
2923 */
2924
2925
2926 /**
2927 \brief Get Debug Authentication Status Register
2928 \details Reads Debug Authentication Status register.
2929 \return Debug Authentication Status Register.
2930 */
DIB_GetAuthStatus(void)2931 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
2932 {
2933 return (DIB->DAUTHSTATUS);
2934 }
2935
2936
2937 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2938 /**
2939 \brief Get Debug Authentication Status Register (non-secure)
2940 \details Reads non-secure Debug Authentication Status register when in secure state.
2941 \return Debug Authentication Status Register.
2942 */
TZ_DIB_GetAuthStatus_NS(void)2943 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
2944 {
2945 return (DIB_NS->DAUTHSTATUS);
2946 }
2947 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2948
2949 /*@} end of CMSIS_Core_DCBFunctions */
2950
2951
2952
2953
2954 /* ################################## SysTick function ############################################ */
2955 /**
2956 \ingroup CMSIS_Core_FunctionInterface
2957 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2958 \brief Functions that configure the System.
2959 @{
2960 */
2961
2962 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2963
2964 /**
2965 \brief System Tick Configuration
2966 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2967 Counter is in free running mode to generate periodic interrupts.
2968 \param [in] ticks Number of ticks between two interrupts.
2969 \return 0 Function succeeded.
2970 \return 1 Function failed.
2971 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2972 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2973 must contain a vendor-specific implementation of this function.
2974 */
SysTick_Config(uint32_t ticks)2975 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2976 {
2977 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2978 {
2979 return (1UL); /* Reload value impossible */
2980 }
2981
2982 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2983 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2984 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2985 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2986 SysTick_CTRL_TICKINT_Msk |
2987 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2988 return (0UL); /* Function successful */
2989 }
2990
2991 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2992 /**
2993 \brief System Tick Configuration (non-secure)
2994 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2995 Counter is in free running mode to generate periodic interrupts.
2996 \param [in] ticks Number of ticks between two interrupts.
2997 \return 0 Function succeeded.
2998 \return 1 Function failed.
2999 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3000 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
3001 must contain a vendor-specific implementation of this function.
3002
3003 */
TZ_SysTick_Config_NS(uint32_t ticks)3004 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3005 {
3006 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3007 {
3008 return (1UL); /* Reload value impossible */
3009 }
3010
3011 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3012 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3013 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3014 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3015 SysTick_CTRL_TICKINT_Msk |
3016 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3017 return (0UL); /* Function successful */
3018 }
3019 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3020
3021 #endif
3022
3023 /*@} end of CMSIS_Core_SysTickFunctions */
3024
3025
3026
3027 /* ##################################### Debug In/Output function ########################################### */
3028 /**
3029 \ingroup CMSIS_Core_FunctionInterface
3030 \defgroup CMSIS_core_DebugFunctions ITM Functions
3031 \brief Functions that access the ITM debug interface.
3032 @{
3033 */
3034
3035 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
3036 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
3037
3038
3039 /**
3040 \brief ITM Send Character
3041 \details Transmits a character via the ITM channel 0, and
3042 \li Just returns when no debugger is connected that has booked the output.
3043 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
3044 \param [in] ch Character to transmit.
3045 \returns Character to transmit.
3046 */
ITM_SendChar(uint32_t ch)3047 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3048 {
3049 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3050 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3051 {
3052 while (ITM->PORT[0U].u32 == 0UL)
3053 {
3054 __NOP();
3055 }
3056 ITM->PORT[0U].u8 = (uint8_t)ch;
3057 }
3058 return (ch);
3059 }
3060
3061
3062 /**
3063 \brief ITM Receive Character
3064 \details Inputs a character via the external variable \ref ITM_RxBuffer.
3065 \return Received character.
3066 \return -1 No character pending.
3067 */
ITM_ReceiveChar(void)3068 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
3069 {
3070 int32_t ch = -1; /* no character available */
3071
3072 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3073 {
3074 ch = ITM_RxBuffer;
3075 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3076 }
3077
3078 return (ch);
3079 }
3080
3081
3082 /**
3083 \brief ITM Check Character
3084 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
3085 \return 0 No character available.
3086 \return 1 Character available.
3087 */
ITM_CheckChar(void)3088 __STATIC_INLINE int32_t ITM_CheckChar (void)
3089 {
3090
3091 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3092 {
3093 return (0); /* no character available */
3094 }
3095 else
3096 {
3097 return (1); /* character available */
3098 }
3099 }
3100
3101 /*@} end of CMSIS_core_DebugFunctions */
3102
3103
3104
3105
3106 #ifdef __cplusplus
3107 }
3108 #endif
3109
3110 #endif /* __CORE_CM35P_H_DEPENDANT */
3111
3112 #endif /* __CMSIS_GENERIC */
3113