1 /*
2 * Copyright (c) 2009-2023 Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Licensed under the Apache License, Version 2.0 (the License); you may
7 * not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 */
18
19 /*
20 * CMSIS Cortex-M4 Core Peripheral Access Layer Header File
21 */
22
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #elif defined (__clang__)
26 #pragma clang system_header /* treat file as system include file */
27 #elif defined ( __GNUC__ )
28 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
29 #endif
30
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M4
60 @{
61 */
62
63 #include "cmsis_version.h"
64
65 /* CMSIS CM4 definitions */
66
67 #define __CORTEX_M (4U) /*!< Cortex-M Core */
68
69 /** __FPU_USED indicates whether an FPU is used or not.
70 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
71 */
72 #if defined ( __CC_ARM )
73 #if defined (__TARGET_FPU_VFP)
74 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
75 #define __FPU_USED 1U
76 #else
77 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
78 #define __FPU_USED 0U
79 #endif
80 #else
81 #define __FPU_USED 0U
82 #endif
83
84 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
85 #if defined (__ARM_FP)
86 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
87 #define __FPU_USED 1U
88 #else
89 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
90 #define __FPU_USED 0U
91 #endif
92 #else
93 #define __FPU_USED 0U
94 #endif
95
96 #elif defined (__ti__)
97 #if defined (__ARM_FP)
98 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
99 #define __FPU_USED 1U
100 #else
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #define __FPU_USED 0U
103 #endif
104 #else
105 #define __FPU_USED 0U
106 #endif
107
108 #elif defined ( __GNUC__ )
109 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
110 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
111 #define __FPU_USED 1U
112 #else
113 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
114 #define __FPU_USED 0U
115 #endif
116 #else
117 #define __FPU_USED 0U
118 #endif
119
120 #elif defined ( __ICCARM__ )
121 #if defined (__ARMVFP__)
122 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
123 #define __FPU_USED 1U
124 #else
125 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
126 #define __FPU_USED 0U
127 #endif
128 #else
129 #define __FPU_USED 0U
130 #endif
131
132 #elif defined ( __TI_ARM__ )
133 #if defined (__TI_VFP_SUPPORT__)
134 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
135 #define __FPU_USED 1U
136 #else
137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
138 #define __FPU_USED 0U
139 #endif
140 #else
141 #define __FPU_USED 0U
142 #endif
143
144 #elif defined ( __TASKING__ )
145 #if defined (__FPU_VFP__)
146 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
147 #define __FPU_USED 1U
148 #else
149 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
150 #define __FPU_USED 0U
151 #endif
152 #else
153 #define __FPU_USED 0U
154 #endif
155
156 #elif defined ( __CSMC__ )
157 #if ( __CSMC__ & 0x400U)
158 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
159 #define __FPU_USED 1U
160 #else
161 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
162 #define __FPU_USED 0U
163 #endif
164 #else
165 #define __FPU_USED 0U
166 #endif
167
168 #endif
169
170 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
171
172
173 #ifdef __cplusplus
174 }
175 #endif
176
177 #endif /* __CORE_CM4_H_GENERIC */
178
179 #ifndef __CMSIS_GENERIC
180
181 #ifndef __CORE_CM4_H_DEPENDANT
182 #define __CORE_CM4_H_DEPENDANT
183
184 #ifdef __cplusplus
185 extern "C" {
186 #endif
187
188 /* check device defines and use defaults */
189 #if defined __CHECK_DEVICE_DEFINES
190 #ifndef __CM4_REV
191 #define __CM4_REV 0x0000U
192 #warning "__CM4_REV not defined in device header file; using default!"
193 #endif
194
195 #ifndef __FPU_PRESENT
196 #define __FPU_PRESENT 0U
197 #warning "__FPU_PRESENT not defined in device header file; using default!"
198 #endif
199
200 #ifndef __MPU_PRESENT
201 #define __MPU_PRESENT 0U
202 #warning "__MPU_PRESENT not defined in device header file; using default!"
203 #endif
204
205 #ifndef __VTOR_PRESENT
206 #define __VTOR_PRESENT 1U
207 #warning "__VTOR_PRESENT not defined in device header file; using default!"
208 #endif
209
210 #ifndef __NVIC_PRIO_BITS
211 #define __NVIC_PRIO_BITS 3U
212 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
213 #endif
214
215 #ifndef __Vendor_SysTickConfig
216 #define __Vendor_SysTickConfig 0U
217 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
218 #endif
219 #endif
220
221 /* IO definitions (access restrictions to peripheral registers) */
222 /**
223 \defgroup CMSIS_glob_defs CMSIS Global Defines
224
225 <strong>IO Type Qualifiers</strong> are used
226 \li to specify the access to peripheral variables.
227 \li for automatic generation of peripheral register debug information.
228 */
229 #ifdef __cplusplus
230 #define __I volatile /*!< Defines 'read only' permissions */
231 #else
232 #define __I volatile const /*!< Defines 'read only' permissions */
233 #endif
234 #define __O volatile /*!< Defines 'write only' permissions */
235 #define __IO volatile /*!< Defines 'read / write' permissions */
236
237 /* following defines should be used for structure members */
238 #define __IM volatile const /*! Defines 'read only' structure member permissions */
239 #define __OM volatile /*! Defines 'write only' structure member permissions */
240 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
241
242 /*@} end of group Cortex_M4 */
243
244
245
246 /*******************************************************************************
247 * Register Abstraction
248 Core Register contain:
249 - Core Register
250 - Core NVIC Register
251 - Core SCB Register
252 - Core SysTick Register
253 - Core Debug Register
254 - Core MPU Register
255 - Core FPU Register
256 ******************************************************************************/
257 /**
258 \defgroup CMSIS_core_register Defines and Type Definitions
259 \brief Type definitions and defines for Cortex-M processor based devices.
260 */
261
262 /**
263 \ingroup CMSIS_core_register
264 \defgroup CMSIS_CORE Status and Control Registers
265 \brief Core Register type definitions.
266 @{
267 */
268
269 /**
270 \brief Union type to access the Application Program Status Register (APSR).
271 */
272 typedef union
273 {
274 struct
275 {
276 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
277 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
278 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
279 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
280 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
281 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
282 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
283 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
284 } b; /*!< Structure used for bit access */
285 uint32_t w; /*!< Type used for word access */
286 } APSR_Type;
287
288 /** \brief APSR Register Definitions */
289 #define APSR_N_Pos 31U /*!< APSR: N Position */
290 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
291
292 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
293 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
294
295 #define APSR_C_Pos 29U /*!< APSR: C Position */
296 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
297
298 #define APSR_V_Pos 28U /*!< APSR: V Position */
299 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
300
301 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
302 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
303
304 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
305 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
306
307
308 /**
309 \brief Union type to access the Interrupt Program Status Register (IPSR).
310 */
311 typedef union
312 {
313 struct
314 {
315 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
316 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
317 } b; /*!< Structure used for bit access */
318 uint32_t w; /*!< Type used for word access */
319 } IPSR_Type;
320
321 /** \brief IPSR Register Definitions */
322 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
323 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
324
325
326 /**
327 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
328 */
329 typedef union
330 {
331 struct
332 {
333 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
334 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
335 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
336 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
337 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
338 uint32_t T:1; /*!< bit: 24 Thumb bit */
339 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
340 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
341 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
342 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
343 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
344 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
345 } b; /*!< Structure used for bit access */
346 uint32_t w; /*!< Type used for word access */
347 } xPSR_Type;
348
349 /** \brief xPSR Register Definitions */
350 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
351 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
352
353 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
354 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
355
356 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
357 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
358
359 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
360 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
361
362 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
363 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
364
365 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
366 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
367
368 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
369 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
370
371 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
372 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
373
374 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
375 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
376
377 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
378 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
379
380
381 /**
382 \brief Union type to access the Control Registers (CONTROL).
383 */
384 typedef union
385 {
386 struct
387 {
388 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
389 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
390 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
391 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
392 } b; /*!< Structure used for bit access */
393 uint32_t w; /*!< Type used for word access */
394 } CONTROL_Type;
395
396 /** \brief CONTROL Register Definitions */
397 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
398 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
399
400 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
401 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
402
403 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
404 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
405
406 /*@} end of group CMSIS_CORE */
407
408
409 /**
410 \ingroup CMSIS_core_register
411 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
412 \brief Type definitions for the NVIC Registers
413 @{
414 */
415
416 /**
417 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
418 */
419 typedef struct
420 {
421 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
422 uint32_t RESERVED0[24U];
423 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
424 uint32_t RESERVED1[24U];
425 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
426 uint32_t RESERVED2[24U];
427 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
428 uint32_t RESERVED3[24U];
429 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
430 uint32_t RESERVED4[56U];
431 __IOM uint8_t IPR[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
432 uint32_t RESERVED5[644U];
433 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
434 } NVIC_Type;
435
436 /** \brief NVIC Software Triggered Interrupt Register Definitions */
437 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
438 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
439
440 /*@} end of group CMSIS_NVIC */
441
442
443 /**
444 \ingroup CMSIS_core_register
445 \defgroup CMSIS_SCB System Control Block (SCB)
446 \brief Type definitions for the System Control Block Registers
447 @{
448 */
449
450 /**
451 \brief Structure type to access the System Control Block (SCB).
452 */
453 typedef struct
454 {
455 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
456 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
457 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
458 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
459 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
460 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
461 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
462 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
463 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
464 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
465 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
466 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
467 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
468 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
469 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
470 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
471 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
472 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
473 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
474 uint32_t RESERVED0[5U];
475 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
476 uint32_t RESERVED3[93U];
477 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
478 } SCB_Type;
479
480 /** \brief SCB CPUID Register Definitions */
481 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
482 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
483
484 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
485 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
486
487 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
488 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
489
490 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
491 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
492
493 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
494 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
495
496 /** \brief SCB Interrupt Control State Register Definitions */
497 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
498 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
499
500 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
501 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
502
503 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
504 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
505
506 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
507 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
508
509 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
510 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
511
512 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
513 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
514
515 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
516 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
517
518 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
519 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
520
521 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
522 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
523
524 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
525 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
526
527 /** \brief SCB Vector Table Offset Register Definitions */
528 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
529 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
530
531 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
532 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
533 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
534
535 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
536 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
537
538 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
539 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
540
541 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
542 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
543
544 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
545 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
546
547 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
548 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
549
550 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
551 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
552
553 /** \brief SCB System Control Register Definitions */
554 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
555 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
556
557 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
558 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
559
560 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
561 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
562
563 /** \brief SCB Configuration Control Register Definitions */
564 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
565 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
566
567 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
568 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
569
570 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
571 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
572
573 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
574 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
575
576 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
577 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
578
579 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
580 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
581
582 /** \brief SCB System Handler Control and State Register Definitions */
583 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
584 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
585
586 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
587 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
588
589 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
590 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
591
592 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
593 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
594
595 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
596 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
597
598 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
599 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
600
601 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
602 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
603
604 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
605 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
606
607 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
608 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
609
610 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
611 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
612
613 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
614 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
615
616 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
617 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
618
619 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
620 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
621
622 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
623 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
624
625 /** \brief SCB Configurable Fault Status Register Definitions */
626 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
627 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
628
629 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
630 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
631
632 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
633 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
634
635 /** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */
636 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
637 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
638
639 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
640 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
641
642 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
643 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
644
645 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
646 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
647
648 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
649 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
650
651 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
652 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
653
654 /** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
655 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
656 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
657
658 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
659 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
660
661 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
662 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
663
664 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
665 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
666
667 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
668 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
669
670 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
671 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
672
673 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
674 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
675
676 /** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
677 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
678 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
679
680 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
681 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
682
683 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
684 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
685
686 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
687 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
688
689 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
690 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
691
692 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
693 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
694
695 /** \brief SCB Hard Fault Status Register Definitions */
696 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
697 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
698
699 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
700 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
701
702 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
703 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
704
705 /** \brief SCB Debug Fault Status Register Definitions */
706 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
707 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
708
709 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
710 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
711
712 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
713 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
714
715 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
716 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
717
718 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
719 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
720
721 /*@} end of group CMSIS_SCB */
722
723
724 /**
725 \ingroup CMSIS_core_register
726 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
727 \brief Type definitions for the System Control and ID Register not in the SCB
728 @{
729 */
730
731 /**
732 \brief Structure type to access the System Control and ID Register not in the SCB.
733 */
734 typedef struct
735 {
736 uint32_t RESERVED0[1U];
737 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
738 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
739 } SCnSCB_Type;
740
741 /** \brief SCnSCB Interrupt Controller Type Register Definitions */
742 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
743 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
744
745 /** \brief SCnSCB Auxiliary Control Register Definitions */
746 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
747 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
748
749 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
750 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
751
752 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
753 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
754
755 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
756 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
757
758 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
759 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
760
761 /*@} end of group CMSIS_SCnotSCB */
762
763
764 /**
765 \ingroup CMSIS_core_register
766 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
767 \brief Type definitions for the System Timer Registers.
768 @{
769 */
770
771 /**
772 \brief Structure type to access the System Timer (SysTick).
773 */
774 typedef struct
775 {
776 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
777 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
778 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
779 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
780 } SysTick_Type;
781
782 /** \brief SysTick Control / Status Register Definitions */
783 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
784 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
785
786 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
787 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
788
789 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
790 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
791
792 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
793 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
794
795 /** \brief SysTick Reload Register Definitions */
796 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
797 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
798
799 /** \brief SysTick Current Register Definitions */
800 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
801 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
802
803 /** \brief SysTick Calibration Register Definitions */
804 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
805 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
806
807 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
808 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
809
810 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
811 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
812
813 /*@} end of group CMSIS_SysTick */
814
815
816 /**
817 \ingroup CMSIS_core_register
818 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
819 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
820 @{
821 */
822
823 /**
824 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
825 */
826 typedef struct
827 {
828 __OM union
829 {
830 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
831 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
832 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
833 } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */
834 uint32_t RESERVED0[864U];
835 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */
836 uint32_t RESERVED1[15U];
837 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */
838 uint32_t RESERVED2[15U];
839 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */
840 uint32_t RESERVED3[32U];
841 uint32_t RESERVED4[43U];
842 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */
843 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */
844 } ITM_Type;
845
846 /** \brief ITM Trace Privilege Register Definitions */
847 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
848 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
849
850 /** \brief ITM Trace Control Register Definitions */
851 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
852 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
853
854 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
855 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
856
857 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
858 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
859
860 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPrescale Position */
861 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPrescale Mask */
862
863 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
864 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
865
866 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
867 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
868
869 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
870 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
871
872 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
873 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
874
875 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
876 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
877
878 /** \brief ITM Lock Status Register Definitions */
879 #define ITM_LSR_BYTEACC_Pos 2U /*!< ITM LSR: ByteAcc Position */
880 #define ITM_LSR_BYTEACC_Msk (1UL << ITM_LSR_BYTEACC_Pos) /*!< ITM LSR: ByteAcc Mask */
881
882 #define ITM_LSR_ACCESS_Pos 1U /*!< ITM LSR: Access Position */
883 #define ITM_LSR_ACCESS_Msk (1UL << ITM_LSR_ACCESS_Pos) /*!< ITM LSR: Access Mask */
884
885 #define ITM_LSR_PRESENT_Pos 0U /*!< ITM LSR: Present Position */
886 #define ITM_LSR_PRESENT_Msk (1UL /*<< ITM_LSR_PRESENT_Pos*/) /*!< ITM LSR: Present Mask */
887
888 /*@}*/ /* end of group CMSIS_ITM */
889
890
891 /**
892 \ingroup CMSIS_core_register
893 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
894 \brief Type definitions for the Data Watchpoint and Trace (DWT)
895 @{
896 */
897
898 /**
899 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
900 */
901 typedef struct
902 {
903 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
904 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
905 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
906 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
907 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
908 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
909 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
910 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
911 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
912 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
913 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
914 uint32_t RESERVED0[1U];
915 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
916 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
917 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
918 uint32_t RESERVED1[1U];
919 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
920 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
921 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
922 uint32_t RESERVED2[1U];
923 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
924 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
925 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
926 } DWT_Type;
927
928 /** \brief DWT Control Register Definitions */
929 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
930 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
931
932 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
933 #define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
934
935 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
936 #define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
937
938 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
939 #define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
940
941 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
942 #define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
943
944 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
945 #define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
946
947 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
948 #define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
949
950 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
951 #define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
952
953 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
954 #define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
955
956 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
957 #define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
958
959 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
960 #define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
961
962 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
963 #define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
964
965 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
966 #define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
967
968 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
969 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
970
971 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
972 #define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
973
974 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
975 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
976
977 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
978 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
979
980 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
981 #define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
982
983 /** \brief DWT CPI Count Register Definitions */
984 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
985 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
986
987 /** \brief DWT Exception Overhead Count Register Definitions */
988 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
989 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
990
991 /** \brief DWT Sleep Count Register Definitions */
992 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
993 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
994
995 /** \brief DWT LSU Count Register Definitions */
996 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
997 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
998
999 /** \brief DWT Folded-instruction Count Register Definitions */
1000 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1001 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1002
1003 /** \brief DWT Comparator Mask Register Definitions */
1004 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1005 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1006
1007 /** \brief DWT Comparator Function Register Definitions */
1008 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1009 #define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1010
1011 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1012 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1013
1014 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1015 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1016
1017 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1018 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1019
1020 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1021 #define DWT_FUNCTION_LNK1ENA_Msk (1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1022
1023 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1024 #define DWT_FUNCTION_DATAVMATCH_Msk (1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1025
1026 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1027 #define DWT_FUNCTION_CYCMATCH_Msk (1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1028
1029 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1030 #define DWT_FUNCTION_EMITRANGE_Msk (1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1031
1032 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1033 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1034
1035 /*@}*/ /* end of group CMSIS_DWT */
1036
1037
1038 /**
1039 \ingroup CMSIS_core_register
1040 \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU)
1041 \brief Type definitions for the Trace Port Interface Unit (TPIU)
1042 @{
1043 */
1044
1045 /**
1046 \brief Structure type to access the Trace Port Interface Unit Register (TPIU).
1047 */
1048 typedef struct
1049 {
1050 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1051 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1052 uint32_t RESERVED0[2U];
1053 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1054 uint32_t RESERVED1[55U];
1055 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1056 uint32_t RESERVED2[131U];
1057 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1058 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1059 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1060 uint32_t RESERVED3[759U];
1061 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1062 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1063 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1064 uint32_t RESERVED4[1U];
1065 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1066 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1067 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1068 uint32_t RESERVED5[39U];
1069 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1070 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1071 uint32_t RESERVED7[8U];
1072 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
1073 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1074 } TPIU_Type;
1075
1076 /** \brief TPIU Asynchronous Clock Prescaler Register Definitions */
1077 #define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */
1078 #define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */
1079
1080 /** \brief TPIU Selected Pin Protocol Register Definitions */
1081 #define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */
1082 #define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */
1083
1084 /** \brief TPIU Formatter and Flush Status Register Definitions */
1085 #define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */
1086 #define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */
1087
1088 #define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */
1089 #define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */
1090
1091 #define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */
1092 #define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */
1093
1094 #define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */
1095 #define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */
1096
1097 /** \brief TPIU Formatter and Flush Control Register Definitions */
1098 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */
1099 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */
1100
1101 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */
1102 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
1103
1104 /** \brief TPIU TRIGGER Register Definitions */
1105 #define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */
1106 #define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */
1107
1108 /** \brief TPIU Integration ETM Data Register Definitions (FIFO0) */
1109 #define TPIU_FIFO0_ITM_ATVALID_Pos 29U /*!< TPIU FIFO0: ITM_ATVALID Position */
1110 #define TPIU_FIFO0_ITM_ATVALID_Msk (1UL << TPIU_FIFO0_ITM_ATVALID_Pos) /*!< TPIU FIFO0: ITM_ATVALID Mask */
1111
1112 #define TPIU_FIFO0_ITM_bytecount_Pos 27U /*!< TPIU FIFO0: ITM_bytecount Position */
1113 #define TPIU_FIFO0_ITM_bytecount_Msk (0x3UL << TPIU_FIFO0_ITM_bytecount_Pos) /*!< TPIU FIFO0: ITM_bytecount Mask */
1114
1115 #define TPIU_FIFO0_ETM_ATVALID_Pos 26U /*!< TPIU FIFO0: ETM_ATVALID Position */
1116 #define TPIU_FIFO0_ETM_ATVALID_Msk (1UL << TPIU_FIFO0_ETM_ATVALID_Pos) /*!< TPIU FIFO0: ETM_ATVALID Mask */
1117
1118 #define TPIU_FIFO0_ETM_bytecount_Pos 24U /*!< TPIU FIFO0: ETM_bytecount Position */
1119 #define TPIU_FIFO0_ETM_bytecount_Msk (0x3UL << TPIU_FIFO0_ETM_bytecount_Pos) /*!< TPIU FIFO0: ETM_bytecount Mask */
1120
1121 #define TPIU_FIFO0_ETM2_Pos 16U /*!< TPIU FIFO0: ETM2 Position */
1122 #define TPIU_FIFO0_ETM2_Msk (0xFFUL << TPIU_FIFO0_ETM2_Pos) /*!< TPIU FIFO0: ETM2 Mask */
1123
1124 #define TPIU_FIFO0_ETM1_Pos 8U /*!< TPIU FIFO0: ETM1 Position */
1125 #define TPIU_FIFO0_ETM1_Msk (0xFFUL << TPIU_FIFO0_ETM1_Pos) /*!< TPIU FIFO0: ETM1 Mask */
1126
1127 #define TPIU_FIFO0_ETM0_Pos 0U /*!< TPIU FIFO0: ETM0 Position */
1128 #define TPIU_FIFO0_ETM0_Msk (0xFFUL /*<< TPIU_FIFO0_ETM0_Pos*/) /*!< TPIU FIFO0: ETM0 Mask */
1129
1130 /** \brief TPIU ITATBCTR2 Register Definitions */
1131 #define TPIU_ITATBCTR2_ATREADY2_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2 Position */
1132 #define TPIU_ITATBCTR2_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2 Mask */
1133
1134 #define TPIU_ITATBCTR2_ATREADY1_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1 Position */
1135 #define TPIU_ITATBCTR2_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1 Mask */
1136
1137 /** \brief TPIU Integration ITM Data Register Definitions (FIFO1) */
1138 #define TPIU_FIFO1_ITM_ATVALID_Pos 29U /*!< TPIU FIFO1: ITM_ATVALID Position */
1139 #define TPIU_FIFO1_ITM_ATVALID_Msk (1UL << TPIU_FIFO1_ITM_ATVALID_Pos) /*!< TPIU FIFO1: ITM_ATVALID Mask */
1140
1141 #define TPIU_FIFO1_ITM_bytecount_Pos 27U /*!< TPIU FIFO1: ITM_bytecount Position */
1142 #define TPIU_FIFO1_ITM_bytecount_Msk (0x3UL << TPIU_FIFO1_ITM_bytecount_Pos) /*!< TPIU FIFO1: ITM_bytecount Mask */
1143
1144 #define TPIU_FIFO1_ETM_ATVALID_Pos 26U /*!< TPIU FIFO1: ETM_ATVALID Position */
1145 #define TPIU_FIFO1_ETM_ATVALID_Msk (1UL << TPIU_FIFO1_ETM_ATVALID_Pos) /*!< TPIU FIFO1: ETM_ATVALID Mask */
1146
1147 #define TPIU_FIFO1_ETM_bytecount_Pos 24U /*!< TPIU FIFO1: ETM_bytecount Position */
1148 #define TPIU_FIFO1_ETM_bytecount_Msk (0x3UL << TPIU_FIFO1_ETM_bytecount_Pos) /*!< TPIU FIFO1: ETM_bytecount Mask */
1149
1150 #define TPIU_FIFO1_ITM2_Pos 16U /*!< TPIU FIFO1: ITM2 Position */
1151 #define TPIU_FIFO1_ITM2_Msk (0xFFUL << TPIU_FIFO1_ITM2_Pos) /*!< TPIU FIFO1: ITM2 Mask */
1152
1153 #define TPIU_FIFO1_ITM1_Pos 8U /*!< TPIU FIFO1: ITM1 Position */
1154 #define TPIU_FIFO1_ITM1_Msk (0xFFUL << TPIU_FIFO1_ITM1_Pos) /*!< TPIU FIFO1: ITM1 Mask */
1155
1156 #define TPIU_FIFO1_ITM0_Pos 0U /*!< TPIU FIFO1: ITM0 Position */
1157 #define TPIU_FIFO1_ITM0_Msk (0xFFUL /*<< TPIU_FIFO1_ITM0_Pos*/) /*!< TPIU FIFO1: ITM0 Mask */
1158
1159 /** \brief TPIU ITATBCTR0 Register Definitions */
1160 #define TPIU_ITATBCTR0_ATREADY2_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2 Position */
1161 #define TPIU_ITATBCTR0_ATREADY2_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2 Mask */
1162
1163 #define TPIU_ITATBCTR0_ATREADY1_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1 Position */
1164 #define TPIU_ITATBCTR0_ATREADY1_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1 Mask */
1165
1166 /** \brief TPIU Integration Mode Control Register Definitions */
1167 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */
1168 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
1169
1170 /** \brief TPIU DEVID Register Definitions */
1171 #define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */
1172 #define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */
1173
1174 #define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */
1175 #define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */
1176
1177 #define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */
1178 #define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */
1179
1180 #define TPIU_DEVID_MinBufSz_Pos 6U /*!< TPIU DEVID: MinBufSz Position */
1181 #define TPIU_DEVID_MinBufSz_Msk (0x7UL << TPIU_DEVID_MinBufSz_Pos) /*!< TPIU DEVID: MinBufSz Mask */
1182
1183 #define TPIU_DEVID_AsynClkIn_Pos 5U /*!< TPIU DEVID: AsynClkIn Position */
1184 #define TPIU_DEVID_AsynClkIn_Msk (1UL << TPIU_DEVID_AsynClkIn_Pos) /*!< TPIU DEVID: AsynClkIn Mask */
1185
1186 #define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */
1187 #define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */
1188
1189 /** \brief TPIU DEVTYPE Register Definitions */
1190 #define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */
1191 #define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */
1192
1193 #define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */
1194 #define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
1195
1196 /*@}*/ /* end of group CMSIS_TPIU */
1197
1198
1199 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1200 /**
1201 \ingroup CMSIS_core_register
1202 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1203 \brief Type definitions for the Memory Protection Unit (MPU)
1204 @{
1205 */
1206
1207 /**
1208 \brief Structure type to access the Memory Protection Unit (MPU).
1209 */
1210 typedef struct
1211 {
1212 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1213 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1214 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1215 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1216 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1217 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1218 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1219 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1220 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1221 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1222 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1223 } MPU_Type;
1224
1225 #define MPU_TYPE_RALIASES 4U
1226
1227 /** \brief MPU Type Register Definitions */
1228 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1229 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1230
1231 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1232 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1233
1234 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1235 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1236
1237 /** \brief MPU Control Register Definitions */
1238 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1239 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1240
1241 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1242 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1243
1244 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1245 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1246
1247 /** \brief MPU Region Number Register Definitions */
1248 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1249 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1250
1251 /** \brief MPU Region Base Address Register Definitions */
1252 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1253 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1254
1255 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1256 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1257
1258 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1259 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1260
1261 /** \brief MPU Region Attribute and Size Register Definitions */
1262 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1263 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1264
1265 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1266 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1267
1268 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1269 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1270
1271 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1272 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1273
1274 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1275 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1276
1277 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1278 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1279
1280 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1281 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1282
1283 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1284 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1285
1286 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1287 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1288
1289 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1290 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1291
1292 /*@} end of group CMSIS_MPU */
1293 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1294
1295
1296 /**
1297 \ingroup CMSIS_core_register
1298 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1299 \brief Type definitions for the Floating Point Unit (FPU)
1300 @{
1301 */
1302
1303 /**
1304 \brief Structure type to access the Floating Point Unit (FPU).
1305 */
1306 typedef struct
1307 {
1308 uint32_t RESERVED0[1U];
1309 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1310 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1311 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1312 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
1313 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
1314 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
1315 } FPU_Type;
1316
1317 /** \brief FPU Floating-Point Context Control Register Definitions */
1318 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1319 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1320
1321 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1322 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1323
1324 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1325 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1326
1327 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1328 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1329
1330 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1331 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1332
1333 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1334 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1335
1336 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1337 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1338
1339 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1340 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1341
1342 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1343 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1344
1345 /** \brief FPU Floating-Point Context Address Register Definitions */
1346 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1347 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1348
1349 /** \brief FPU Floating-Point Default Status Control Register Definitions */
1350 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1351 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1352
1353 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1354 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1355
1356 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1357 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1358
1359 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1360 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1361
1362 /** \brief FPU Media and VFP Feature Register 0 Definitions */
1363 #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */
1364 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */
1365
1366 #define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */
1367 #define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */
1368
1369 #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */
1370 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */
1371
1372 #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */
1373 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
1374
1375 #define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */
1376 #define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */
1377
1378 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */
1379 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
1380
1381 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */
1382 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
1383
1384 #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */
1385 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */
1386
1387 /** \brief FPU Media and VFP Feature Register 1 Definitions */
1388 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */
1389 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */
1390
1391 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1392 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1393
1394 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1395 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1396
1397 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1398 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1399
1400 /** \brief FPU Media and VFP Feature Register 2 Definitions */
1401 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1402 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1403
1404 /*@} end of group CMSIS_FPU */
1405
1406
1407 /**
1408 \ingroup CMSIS_core_register
1409 \defgroup CMSIS_DCB Debug Control Block
1410 \brief Type definitions for the Debug Control Block Registers
1411 @{
1412 */
1413
1414 /**
1415 \brief Structure type to access the Debug Control Block Registers (DCB).
1416 */
1417 typedef struct
1418 {
1419 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1420 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1421 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1422 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1423 } DCB_Type;
1424
1425 /** \brief DCB Debug Halting Control and Status Register Definitions */
1426 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1427 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1428
1429 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1430 #define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1431
1432 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1433 #define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1434
1435 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1436 #define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1437
1438 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1439 #define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1440
1441 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1442 #define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1443
1444 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1445 #define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1446
1447 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1448 #define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1449
1450 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1451 #define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1452
1453 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1454 #define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1455
1456 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1457 #define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1458
1459 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1460 #define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1461
1462 /** \brief DCB Debug Core Register Selector Register Definitions */
1463 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1464 #define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1465
1466 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1467 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1468
1469 /** \brief DCB Debug Core Register Data Register Definitions */
1470 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1471 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1472
1473 /** \brief DCB Debug Exception and Monitor Control Register Definitions */
1474 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1475 #define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1476
1477 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
1478 #define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
1479
1480 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
1481 #define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
1482
1483 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
1484 #define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
1485
1486 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
1487 #define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
1488
1489 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1490 #define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1491
1492 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
1493 #define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
1494
1495 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
1496 #define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
1497
1498 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
1499 #define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
1500
1501 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
1502 #define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
1503
1504 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
1505 #define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
1506
1507 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
1508 #define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
1509
1510 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1511 #define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1512
1513 /*@} end of group CMSIS_DCB */
1514
1515
1516 /**
1517 \ingroup CMSIS_core_register
1518 \defgroup CMSIS_core_bitfield Core register bit field macros
1519 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1520 @{
1521 */
1522
1523 /**
1524 \brief Mask and shift a bit field value for use in a register bit range.
1525 \param[in] field Name of the register bit field.
1526 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1527 \return Masked and shifted value.
1528 */
1529 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1530
1531 /**
1532 \brief Mask and shift a register value to extract a bit filed value.
1533 \param[in] field Name of the register bit field.
1534 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1535 \return Masked and shifted bit field value.
1536 */
1537 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1538
1539 /*@} end of group CMSIS_core_bitfield */
1540
1541
1542 /**
1543 \ingroup CMSIS_core_register
1544 \defgroup CMSIS_core_base Core Definitions
1545 \brief Definitions for base addresses, unions, and structures.
1546 @{
1547 */
1548
1549 /* Memory mapping of Core Hardware */
1550 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1551 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1552 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1553 #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */
1554 #define DCB_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1555 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1556 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1557 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1558
1559 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1560 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1561 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1562 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1563 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1564 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1565 #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
1566 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
1567
1568 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1569 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1570 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1571 #endif
1572
1573 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1574 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1575
1576 /*@} */
1577
1578
1579 /**
1580 \ingroup CMSIS_core_register
1581 \defgroup CMSIS_register_aliases Backwards Compatibility Aliases
1582 \brief Register alias definitions for backwards compatibility.
1583 @{
1584 */
1585
1586 /*@} */
1587
1588
1589 /*******************************************************************************
1590 * Hardware Abstraction Layer
1591 Core Function Interface contains:
1592 - Core NVIC Functions
1593 - Core SysTick Functions
1594 - Core Debug Functions
1595 - Core Register Access Functions
1596 ******************************************************************************/
1597 /**
1598 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1599 */
1600
1601
1602
1603 /* ########################## NVIC functions #################################### */
1604 /**
1605 \ingroup CMSIS_Core_FunctionInterface
1606 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1607 \brief Functions that manage interrupts and exceptions via the NVIC.
1608 @{
1609 */
1610
1611 #ifdef CMSIS_NVIC_VIRTUAL
1612 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1613 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1614 #endif
1615 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1616 #else
1617 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1618 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1619 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1620 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1621 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1622 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1623 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1624 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1625 #define NVIC_GetActive __NVIC_GetActive
1626 #define NVIC_SetPriority __NVIC_SetPriority
1627 #define NVIC_GetPriority __NVIC_GetPriority
1628 #define NVIC_SystemReset __NVIC_SystemReset
1629 #endif /* CMSIS_NVIC_VIRTUAL */
1630
1631 #ifdef CMSIS_VECTAB_VIRTUAL
1632 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1633 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1634 #endif
1635 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1636 #else
1637 #define NVIC_SetVector __NVIC_SetVector
1638 #define NVIC_GetVector __NVIC_GetVector
1639 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1640
1641 #define NVIC_USER_IRQ_OFFSET 16
1642
1643
1644 /* The following EXC_RETURN values are saved the LR on exception entry */
1645 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1646 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1647 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1648 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1649 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1650 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1651
1652
1653 /**
1654 \brief Set Priority Grouping
1655 \details Sets the priority grouping field using the required unlock sequence.
1656 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1657 Only values from 0..7 are used.
1658 In case of a conflict between priority grouping and available
1659 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1660 \param [in] PriorityGroup Priority grouping field.
1661 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1662 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1663 {
1664 uint32_t reg_value;
1665 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1666
1667 reg_value = SCB->AIRCR; /* read old register configuration */
1668 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1669 reg_value = (reg_value |
1670 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1671 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1672 SCB->AIRCR = reg_value;
1673 }
1674
1675
1676 /**
1677 \brief Get Priority Grouping
1678 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1679 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1680 */
__NVIC_GetPriorityGrouping(void)1681 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1682 {
1683 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1684 }
1685
1686
1687 /**
1688 \brief Enable Interrupt
1689 \details Enables a device specific interrupt in the NVIC interrupt controller.
1690 \param [in] IRQn Device specific interrupt number.
1691 \note IRQn must not be negative.
1692 */
__NVIC_EnableIRQ(IRQn_Type IRQn)1693 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1694 {
1695 if ((int32_t)(IRQn) >= 0)
1696 {
1697 __COMPILER_BARRIER();
1698 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1699 __COMPILER_BARRIER();
1700 }
1701 }
1702
1703
1704 /**
1705 \brief Get Interrupt Enable status
1706 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1707 \param [in] IRQn Device specific interrupt number.
1708 \return 0 Interrupt is not enabled.
1709 \return 1 Interrupt is enabled.
1710 \note IRQn must not be negative.
1711 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)1712 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1713 {
1714 if ((int32_t)(IRQn) >= 0)
1715 {
1716 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1717 }
1718 else
1719 {
1720 return(0U);
1721 }
1722 }
1723
1724
1725 /**
1726 \brief Disable Interrupt
1727 \details Disables a device specific interrupt in the NVIC interrupt controller.
1728 \param [in] IRQn Device specific interrupt number.
1729 \note IRQn must not be negative.
1730 */
__NVIC_DisableIRQ(IRQn_Type IRQn)1731 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1732 {
1733 if ((int32_t)(IRQn) >= 0)
1734 {
1735 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1736 __DSB();
1737 __ISB();
1738 }
1739 }
1740
1741
1742 /**
1743 \brief Get Pending Interrupt
1744 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1745 \param [in] IRQn Device specific interrupt number.
1746 \return 0 Interrupt status is not pending.
1747 \return 1 Interrupt status is pending.
1748 \note IRQn must not be negative.
1749 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)1750 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1751 {
1752 if ((int32_t)(IRQn) >= 0)
1753 {
1754 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1755 }
1756 else
1757 {
1758 return(0U);
1759 }
1760 }
1761
1762
1763 /**
1764 \brief Set Pending Interrupt
1765 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1766 \param [in] IRQn Device specific interrupt number.
1767 \note IRQn must not be negative.
1768 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)1769 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1770 {
1771 if ((int32_t)(IRQn) >= 0)
1772 {
1773 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1774 }
1775 }
1776
1777
1778 /**
1779 \brief Clear Pending Interrupt
1780 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1781 \param [in] IRQn Device specific interrupt number.
1782 \note IRQn must not be negative.
1783 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)1784 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1785 {
1786 if ((int32_t)(IRQn) >= 0)
1787 {
1788 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1789 }
1790 }
1791
1792
1793 /**
1794 \brief Get Active Interrupt
1795 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1796 \param [in] IRQn Device specific interrupt number.
1797 \return 0 Interrupt status is not active.
1798 \return 1 Interrupt status is active.
1799 \note IRQn must not be negative.
1800 */
__NVIC_GetActive(IRQn_Type IRQn)1801 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1802 {
1803 if ((int32_t)(IRQn) >= 0)
1804 {
1805 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1806 }
1807 else
1808 {
1809 return(0U);
1810 }
1811 }
1812
1813
1814 /**
1815 \brief Set Interrupt Priority
1816 \details Sets the priority of a device specific interrupt or a processor exception.
1817 The interrupt number can be positive to specify a device specific interrupt,
1818 or negative to specify a processor exception.
1819 \param [in] IRQn Interrupt number.
1820 \param [in] priority Priority to set.
1821 \note The priority cannot be set for every processor exception.
1822 */
__NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)1823 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1824 {
1825 if ((int32_t)(IRQn) >= 0)
1826 {
1827 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1828 }
1829 else
1830 {
1831 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1832 }
1833 }
1834
1835
1836 /**
1837 \brief Get Interrupt Priority
1838 \details Reads the priority of a device specific interrupt or a processor exception.
1839 The interrupt number can be positive to specify a device specific interrupt,
1840 or negative to specify a processor exception.
1841 \param [in] IRQn Interrupt number.
1842 \return Interrupt Priority.
1843 Value is aligned automatically to the implemented priority bits of the microcontroller.
1844 */
__NVIC_GetPriority(IRQn_Type IRQn)1845 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1846 {
1847
1848 if ((int32_t)(IRQn) >= 0)
1849 {
1850 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1851 }
1852 else
1853 {
1854 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1855 }
1856 }
1857
1858
1859 /**
1860 \brief Encode Priority
1861 \details Encodes the priority for an interrupt with the given priority group,
1862 preemptive priority value, and subpriority value.
1863 In case of a conflict between priority grouping and available
1864 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1865 \param [in] PriorityGroup Used priority group.
1866 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1867 \param [in] SubPriority Subpriority value (starting from 0).
1868 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1869 */
NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)1870 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1871 {
1872 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1873 uint32_t PreemptPriorityBits;
1874 uint32_t SubPriorityBits;
1875
1876 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1877 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1878
1879 return (
1880 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1881 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1882 );
1883 }
1884
1885
1886 /**
1887 \brief Decode Priority
1888 \details Decodes an interrupt priority value with a given priority group to
1889 preemptive priority value and subpriority value.
1890 In case of a conflict between priority grouping and available
1891 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1892 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1893 \param [in] PriorityGroup Used priority group.
1894 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1895 \param [out] pSubPriority Subpriority value (starting from 0).
1896 */
NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)1897 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1898 {
1899 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1900 uint32_t PreemptPriorityBits;
1901 uint32_t SubPriorityBits;
1902
1903 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1904 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1905
1906 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1907 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1908 }
1909
1910
1911 /**
1912 \brief Set Interrupt Vector
1913 \details Sets an interrupt vector in SRAM based interrupt vector table.
1914 The interrupt number can be positive to specify a device specific interrupt,
1915 or negative to specify a processor exception.
1916 VTOR must been relocated to SRAM before.
1917 \param [in] IRQn Interrupt number
1918 \param [in] vector Address of interrupt handler function
1919 */
__NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)1920 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1921 {
1922 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
1923 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1924 /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
1925 }
1926
1927
1928 /**
1929 \brief Get Interrupt Vector
1930 \details Reads an interrupt vector from interrupt vector table.
1931 The interrupt number can be positive to specify a device specific interrupt,
1932 or negative to specify a processor exception.
1933 \param [in] IRQn Interrupt number.
1934 \return Address of interrupt handler function
1935 */
__NVIC_GetVector(IRQn_Type IRQn)1936 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1937 {
1938 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
1939 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1940 }
1941
1942
1943 /**
1944 \brief System Reset
1945 \details Initiates a system reset request to reset the MCU.
1946 */
__NVIC_SystemReset(void)1947 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1948 {
1949 __DSB(); /* Ensure all outstanding memory accesses included
1950 buffered write are completed before reset */
1951 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1952 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1953 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1954 __DSB(); /* Ensure completion of memory access */
1955
1956 for(;;) /* wait until reset */
1957 {
1958 __NOP();
1959 }
1960 }
1961
1962 /*@} end of CMSIS_Core_NVICFunctions */
1963
1964
1965 /* ########################## MPU functions #################################### */
1966
1967 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1968
1969 #include "m-profile/armv7m_mpu.h"
1970
1971 #endif
1972
1973
1974 /* ########################## FPU functions #################################### */
1975 /**
1976 \ingroup CMSIS_Core_FunctionInterface
1977 \defgroup CMSIS_Core_FpuFunctions FPU Functions
1978 \brief Function that provides FPU type.
1979 @{
1980 */
1981
1982 /**
1983 \brief get FPU type
1984 \details returns the FPU type
1985 \returns
1986 - \b 0: No FPU
1987 - \b 1: Single precision FPU
1988 - \b 2: Double + Single precision FPU
1989 */
SCB_GetFPUType(void)1990 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1991 {
1992 uint32_t mvfr0;
1993
1994 mvfr0 = FPU->MVFR0;
1995 if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
1996 {
1997 return 1U; /* Single precision FPU */
1998 }
1999 else
2000 {
2001 return 0U; /* No FPU */
2002 }
2003 }
2004
2005 /*@} end of CMSIS_Core_FpuFunctions */
2006
2007
2008 /* ################################## SysTick function ############################################ */
2009 /**
2010 \ingroup CMSIS_Core_FunctionInterface
2011 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2012 \brief Functions that configure the System.
2013 @{
2014 */
2015
2016 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2017
2018 /**
2019 \brief System Tick Configuration
2020 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2021 Counter is in free running mode to generate periodic interrupts.
2022 \param [in] ticks Number of ticks between two interrupts.
2023 \return 0 Function succeeded.
2024 \return 1 Function failed.
2025 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2026 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2027 must contain a vendor-specific implementation of this function.
2028 */
SysTick_Config(uint32_t ticks)2029 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2030 {
2031 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2032 {
2033 return (1UL); /* Reload value impossible */
2034 }
2035
2036 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2037 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2038 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2039 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2040 SysTick_CTRL_TICKINT_Msk |
2041 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2042 return (0UL); /* Function successful */
2043 }
2044
2045 #endif
2046
2047 /*@} end of CMSIS_Core_SysTickFunctions */
2048
2049
2050
2051 /* ##################################### Debug In/Output function ########################################### */
2052 /**
2053 \ingroup CMSIS_Core_FunctionInterface
2054 \defgroup CMSIS_core_DebugFunctions ITM Functions
2055 \brief Functions that access the ITM debug interface.
2056 @{
2057 */
2058
2059 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
2060 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
2061
2062
2063 /**
2064 \brief ITM Send Character
2065 \details Transmits a character via the ITM channel 0, and
2066 \li Just returns when no debugger is connected that has booked the output.
2067 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
2068 \param [in] ch Character to transmit.
2069 \returns Character to transmit.
2070 */
ITM_SendChar(uint32_t ch)2071 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2072 {
2073 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2074 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2075 {
2076 while (ITM->PORT[0U].u32 == 0UL)
2077 {
2078 __NOP();
2079 }
2080 ITM->PORT[0U].u8 = (uint8_t)ch;
2081 }
2082 return (ch);
2083 }
2084
2085
2086 /**
2087 \brief ITM Receive Character
2088 \details Inputs a character via the external variable \ref ITM_RxBuffer.
2089 \return Received character.
2090 \return -1 No character pending.
2091 */
ITM_ReceiveChar(void)2092 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2093 {
2094 int32_t ch = -1; /* no character available */
2095
2096 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2097 {
2098 ch = ITM_RxBuffer;
2099 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2100 }
2101
2102 return (ch);
2103 }
2104
2105
2106 /**
2107 \brief ITM Check Character
2108 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
2109 \return 0 No character available.
2110 \return 1 Character available.
2111 */
ITM_CheckChar(void)2112 __STATIC_INLINE int32_t ITM_CheckChar (void)
2113 {
2114
2115 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2116 {
2117 return (0); /* no character available */
2118 }
2119 else
2120 {
2121 return (1); /* character available */
2122 }
2123 }
2124
2125 /*@} end of CMSIS_core_DebugFunctions */
2126
2127
2128
2129
2130 #ifdef __cplusplus
2131 }
2132 #endif
2133
2134 #endif /* __CORE_CM4_H_DEPENDANT */
2135
2136 #endif /* __CMSIS_GENERIC */
2137