Searched refs:__IM (Results 1 - 15 of 15) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm35p.h	303 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 523 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 537 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 538 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 539 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 540 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 541 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 542 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 543 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 544 __IM uint32_ [all...]
H A D	core_cm33.h	303 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 523 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 537 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 538 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 539 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 540 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 541 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 542 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 543 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 544 __IM uint32_ [all...]
H A D	core_cm4.h	238 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 455 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 469 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 470 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 471 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 472 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 473 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 737 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 779 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 843 __IM uint32_ [all...]
H A D	core_sc300.h	179 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 382 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 396 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 397 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 398 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 399 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 400 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 661 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 697 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 761 __IM uint32_ [all...]
H A D	core_cm3.h	179 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 382 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 396 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 397 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 398 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 399 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 400 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 666 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 714 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 778 __IM uint32_ [all...]
H A D	core_cm7.h	253 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 470 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 484 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 485 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 486 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 487 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 488 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 490 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 491 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 492 __IM uint32_ [all...]
H A D	core_cm85.h	310 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 554 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 568 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 569 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 570 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 571 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 572 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 573 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 574 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 575 __IM uint32_ [all...]
H A D	core_starmc1.h	314 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 534 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 548 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 549 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 550 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 551 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 552 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 554 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 555 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 556 __IM uint32_ [all...]
H A D	core_cm23.h	200 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 384 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 564 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 620 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ 629 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ 679 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ 686 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ 690 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ 691 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ 694 __IM uint32_ [all...]
H A D	core_cm55.h	310 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 533 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 547 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 548 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 549 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 550 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 551 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 552 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ 553 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ 554 __IM uint32_ [all...]
H A D	core_sc000.h	179 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 494 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 543 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
H A D	core_cm0plus.h	179 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 358 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 478 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 527 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
H A D	core_ca.h	178 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ macro 684 __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ 685 __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ 695 __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ 696 __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ 752 __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 753 __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ 966 __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ 968 __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ 969 __IM uint32_ [all...]
H A D	core_cm1.h	169 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 344 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 480 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
H A D	core_cm0.h	169 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro 344 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 454 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */

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Indexes created Thu Nov 07 10:32:03 CST 2024