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Help
Searched
refs:IABR
(Results
1 - 10
of
10
) sorted by relevance
/third_party/cmsis/CMSIS/Core/Include/
H
A
D
core_cm23.h
362
__IOM uint32_t
IABR
[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
1483
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
1832
return((uint32_t)(((NVIC_NS->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in TZ_NVIC_GetActive_NS()
H
A
D
core_cm4.h
429
__IOM uint32_t
IABR
[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
1805
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
H
A
D
core_sc300.h
356
__IOM uint32_t
IABR
[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
1606
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
H
A
D
core_cm3.h
356
__IOM uint32_t
IABR
[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
1623
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
H
A
D
core_cm35p.h
495
__IOM uint32_t
IABR
[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
2337
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
2710
return((uint32_t)(((NVIC_NS->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in TZ_NVIC_GetActive_NS()
H
A
D
core_cm33.h
495
__IOM uint32_t
IABR
[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
2337
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
2710
return((uint32_t)(((NVIC_NS->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in TZ_NVIC_GetActive_NS()
H
A
D
core_starmc1.h
506
__IOM uint32_t
IABR
[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
2435
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
2829
return((uint32_t)(((NVIC_NS->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in TZ_NVIC_GetActive_NS()
H
A
D
core_cm7.h
444
__IOM uint32_t
IABR
[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
2024
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
H
A
D
core_cm85.h
526
__IOM uint32_t
IABR
[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
3870
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
4243
return((uint32_t)(((NVIC_NS->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in TZ_NVIC_GetActive_NS()
H
A
D
core_cm55.h
505
__IOM uint32_t
IABR
[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
member
3846
return((uint32_t)(((NVIC->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in __NVIC_GetActive()
4219
return((uint32_t)(((NVIC_NS->
IABR
[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
in TZ_NVIC_GetActive_NS()
Completed in 72 milliseconds