Searched refs:FFCR (Results 1 - 10 of 10) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm4.h	1058 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1098 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1099 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1101 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 1102 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_sc300.h	976 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1016 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1017 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1019 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 1020 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_cm3.h	993 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1033 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1034 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1036 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 1037 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_cm23.h	687 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 727 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 728 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 730 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ 731 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ 733 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 734 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_cm35p.h	1281 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1321 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1322 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1324 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ 1325 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ 1327 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 1328 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_cm33.h	1281 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1321 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1322 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1324 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ 1325 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ 1327 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 1328 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_cm7.h	1277 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1317 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1318 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1320 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 1321 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_starmc1.h	1378 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1418 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1419 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1421 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ 1422 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ 1424 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 1425 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_cm85.h	1953 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1993 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1994 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1996 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ 1997 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ 1999 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 2000 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
H A D	core_cm55.h	1929 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ member 1969 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ 1970 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ 1972 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ 1973 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ 1975 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ 1976 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */

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Indexes created Thu Nov 07 10:32:03 CST 2024