Searched refs:DFSR (Results 1 - 9 of 9) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm4.h	465 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 706 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 707 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 709 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 710 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 712 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 713 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 715 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 716 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 718 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR [all...]
H A D	core_sc300.h	392 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 630 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 631 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 633 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 634 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 636 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 637 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 639 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 640 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 642 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR [all...]
H A D	core_cm3.h	392 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 635 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 636 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 638 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 639 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 641 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 642 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 644 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 645 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 647 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR [all...]
H A D	core_cm35p.h	533 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 842 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 843 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 845 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 846 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 848 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 849 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 851 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 852 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 854 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR [all...]
H A D	core_cm33.h	533 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 842 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 843 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 845 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 846 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 848 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 849 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 851 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 852 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 854 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR [all...]
H A D	core_cm7.h	480 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 758 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 759 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 761 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 762 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 764 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 765 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 767 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 768 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 770 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR [all...]
H A D	core_starmc1.h	544 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 860 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 861 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 863 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 864 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 866 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 867 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 869 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ 870 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 872 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR [all...]
H A D	core_cm85.h	564 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 883 #define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ 884 #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ 886 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 887 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 889 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 890 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 892 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 893 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 895 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR [all...]
H A D	core_cm55.h	543 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ member 862 #define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ 863 #define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ 865 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ 866 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 868 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ 869 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 871 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ 872 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 874 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR [all...]

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Indexes created Thu Nov 07 10:32:03 CST 2024