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Searched refs:CTRL (Results 1 - 23 of 23) sorted by relevance

/third_party/musl/porting/liteos_m/kernel/include/sys/
H A Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
10 #define CEOF CTRL('d')
16 #define CINTR CTRL('c')
17 #define CKILL CTRL('u')
20 #define CSUSP CTRL('z')
22 #define CDSUSP CTRL('y')
23 #define CSTART CTRL('q')
24 #define CSTOP CTRL('s')
25 #define CLNEXT CTRL('v')
26 #define CDISCARD CTRL('
[all...]
/third_party/musl/porting/liteos_m_iccarm/kernel/include/sys/
H A Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
10 #define CEOF CTRL('d')
16 #define CINTR CTRL('c')
17 #define CKILL CTRL('u')
20 #define CSUSP CTRL('z')
22 #define CDSUSP CTRL('y')
23 #define CSTART CTRL('q')
24 #define CSTOP CTRL('s')
25 #define CLNEXT CTRL('v')
26 #define CDISCARD CTRL('
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/third_party/musl/porting/uniproton/kernel/include/sys/
H A Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
10 #define CEOF CTRL('d')
16 #define CINTR CTRL('c')
17 #define CKILL CTRL('u')
20 #define CSUSP CTRL('z')
22 #define CDSUSP CTRL('y')
23 #define CSTART CTRL('q')
24 #define CSTOP CTRL('s')
25 #define CLNEXT CTRL('v')
26 #define CDISCARD CTRL('
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/third_party/musl/include/sys/
H A Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
10 #define CEOF CTRL('d')
16 #define CINTR CTRL('c')
17 #define CKILL CTRL('u')
20 #define CSUSP CTRL('z')
22 #define CDSUSP CTRL('y')
23 #define CSTART CTRL('q')
24 #define CSTOP CTRL('s')
25 #define CLNEXT CTRL('v')
26 #define CDISCARD CTRL('
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/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv8m_pmu.h198 PMU->CTRL |= PMU_CTRL_ENABLE_Msk; in ARM_PMU_Enable()
206 PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; in ARM_PMU_Disable()
224 PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; in ARM_PMU_CYCCNT_Reset()
232 PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; in ARM_PMU_EVCNTR_ALL_Reset()
H A Darmv8m_mpu.h202 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in ARM_MPU_Enable()
218 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in ARM_MPU_Disable()
230 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in ARM_MPU_Enable_NS()
246 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; in ARM_MPU_Disable_NS()
H A Darmv7m_mpu.h192 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; in ARM_MPU_Enable()
208 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in ARM_MPU_Disable()
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm23.h561 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
568 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
569 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
571 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
572 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
574 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
575 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
577 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
578 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
613 __IOM uint32_t CTRL; /*!< Offse member
858 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
964 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ global() member
[all...]
H A Dcore_sc000.h491 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
498 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
499 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
501 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
502 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
504 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
505 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
507 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
508 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
544 __IOM uint32_t CTRL; /*!< Offse member
[all...]
H A Dcore_cm0plus.h475 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
482 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
483 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
485 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
486 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
488 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
489 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
491 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
492 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
528 __IOM uint32_t CTRL; /*!< Offse member
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H A Dcore_cm35p.h984 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
991 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
992 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
994 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
995 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
997 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
998 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1000 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1001 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1135 __IOM uint32_t CTRL; /*!< Offse member
1452 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
1567 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ global() member
[all...]
H A Dcore_cm33.h984 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
991 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
992 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
994 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
995 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
997 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
998 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1000 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1001 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1135 __IOM uint32_t CTRL; /*!< Offse member
1452 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
1567 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ global() member
[all...]
H A Dcore_cm1.h477 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
484 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
485 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
487 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
488 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
490 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
491 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
493 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
494 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
967 SysTick->CTRL in SysTick_Config()
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H A Dcore_cm0.h451 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
458 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
459 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
461 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
462 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
464 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
465 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
467 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
468 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
942 SysTick->CTRL in SysTick_Config()
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H A Dcore_starmc1.h1045 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
1052 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1053 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1055 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1056 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1058 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1059 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1061 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1062 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1184 __IOM uint32_t CTRL; /*!< Offse member
1549 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
1661 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ global() member
[all...]
H A Dcore_cm4.h776 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
783 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
784 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
786 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
787 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
789 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
790 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
792 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
793 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
903 __IOM uint32_t CTRL; /*!< Offse member
1213 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
[all...]
H A Dcore_sc300.h694 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
701 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
702 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
704 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
705 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
707 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
708 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
710 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
711 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
821 __IOM uint32_t CTRL; /*!< Offse member
1131 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
[all...]
H A Dcore_cm3.h711 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
718 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
719 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
721 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
722 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
724 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
725 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
727 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
728 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
838 __IOM uint32_t CTRL; /*!< Offse member
1148 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
[all...]
H A Dcore_cm85.h1088 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
1095 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1096 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1098 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1099 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1101 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1102 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1104 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1105 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1239 __IOM uint32_t CTRL; /*!< Offse member
2158 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ global() member
2928 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
3043 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ global() member
[all...]
H A Dcore_cm55.h1088 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
1095 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1096 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1098 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1099 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1101 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1102 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1104 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1105 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1239 __IOM uint32_t CTRL; /*!< Offse member
2134 __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ global() member
2904 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
3019 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ global() member
[all...]
H A Dcore_cm7.h995 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ member
1002 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1003 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1005 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1006 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1008 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1009 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1011 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1012 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1122 __IOM uint32_t CTRL; /*!< Offse member
1432 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ global() member
[all...]
/third_party/curl/tests/server/
H A Dsws.c1390 #define data_or_ctrl(x) ((x)?"DATA":"CTRL")
1392 #define CTRL 0 macro
1413 int max_tunnel_idx; /* CTRL or DATA */ in http_connect()
1419 clientfd[CTRL] = *infdp; in http_connect()
1429 serverfd[CTRL] = connect_to(ipaddr, ipport); in http_connect()
1430 if(serverfd[CTRL] == CURL_SOCKET_BAD) in http_connect()
1438 max_tunnel_idx = CTRL; in http_connect()
1454 poll_client_rd[CTRL] && poll_client_wr[CTRL] && in http_connect()
1455 poll_server_rd[CTRL] in http_connect()
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/third_party/python/Modules/
H A Dtermios.c5 /* Apparently, on SGI, termios.h won't define CTRL if _XOPEN_SOURCE
8 #define CTRL(c) ((c)&037) macro

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