| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_rlc.c | 40 if (adev->gfx.rlc.in_safe_mode[xcc_id]) in amdgpu_gfx_rlc_enter_safe_mode()
44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true; in amdgpu_gfx_rlc_enter_safe_mode()
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id])) in amdgpu_gfx_rlc_exit_safe_mode()
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false; in amdgpu_gfx_rlc_exit_safe_mode()
86 * Allocate and setup value to save restore block of rlc.
100 &adev->gfx.rlc in amdgpu_gfx_rlc_init_sr()
[all...] |
| H A D | amdgpu_ucode.c | 799 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
800 ucode_addr = adev->gfx.rlc.save_restore_list_cntl; in amdgpu_ucode_init_single_fw()
803 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; in amdgpu_ucode_init_single_fw()
804 ucode_addr = adev->gfx.rlc.save_restore_list_gpm; in amdgpu_ucode_init_single_fw()
807 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; in amdgpu_ucode_init_single_fw()
808 ucode_addr = adev->gfx.rlc.save_restore_list_srm; in amdgpu_ucode_init_single_fw()
811 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
812 ucode_addr = adev->gfx.rlc.rlc_iram_ucode; in amdgpu_ucode_init_single_fw()
815 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
816 ucode_addr = adev->gfx.rlc in amdgpu_ucode_init_single_fw()
[all...] |
| H A D | gfx_v6_0.c | 2020 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_cp_gfx_start()
2342 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; in gfx_v6_0_rlc_init()
2343 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2346 adev->gfx.rlc.cs_data = si_cs_data; in gfx_v6_0_rlc_init()
2347 src_ptr = adev->gfx.rlc.reg_list; in gfx_v6_0_rlc_init()
2348 dws = adev->gfx.rlc.reg_list_size; in gfx_v6_0_rlc_init()
2349 cs_data = adev->gfx.rlc.cs_data; in gfx_v6_0_rlc_init()
2360 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); in gfx_v6_0_rlc_init()
2361 dws = adev->gfx.rlc.clear_state_size + (256 / 4); in gfx_v6_0_rlc_init()
2366 &adev->gfx.rlc in gfx_v6_0_rlc_init()
2416 gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) gfx_v6_0_update_rlc() argument
[all...] |
| H A D | gfx_v7_0.c | 2485 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
3233 /* allocate rlc buffers */ in gfx_v7_0_rlc_init()
3236 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3237 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3240 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3241 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3245 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3246 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3247 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3249 src_ptr = adev->gfx.rlc in gfx_v7_0_rlc_init()
3324 gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) gfx_v7_0_update_rlc() argument
[all...] |
| H A D | gfx_v8_0.c | 936 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
1055 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1057 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1059 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1061 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1063 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1065 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1067 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1069 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1071 adev->gfx.rlc in gfx_v8_0_init_microcode()
[all...] |
| H A D | soc15_common.h | 41 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
46 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported) ? \
|
| H A D | gfx_v9_0.c | 1090 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1230 !adev->gfx.rlc.is_rlc_v2_1)) in gfx_v9_0_check_if_need_gfxoff()
1444 if (adev->gfx.rlc.cs_data == NULL) in gfx_v9_0_get_csb_buffer()
1456 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v9_0_get_csb_buffer()
1637 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1645 adev->gfx.rlc.rlcg_reg_access_supported = true; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1653 adev->gfx.rlc.cs_data = gfx9_cs_data; in gfx_v9_0_rlc_init()
1655 cs_data = adev->gfx.rlc.cs_data; in gfx_v9_0_rlc_init()
1666 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ in gfx_v9_0_rlc_init()
2055 if (adev->gfx.rlc in gfx_v9_0_sw_init()
[all...] |
| H A D | gfx_v11_0.c | 448 kfree(adev->gfx.rlc.register_list_format); in gfx_v11_0_free_microcode()
621 if (adev->gfx.rlc.cs_data == NULL) in gfx_v11_0_get_csb_buffer()
633 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v11_0_get_csb_buffer()
664 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v11_0_rlc_fini()
665 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v11_0_rlc_fini()
666 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v11_0_rlc_fini()
669 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v11_0_rlc_fini()
670 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v11_0_rlc_fini()
671 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v11_0_rlc_fini()
678 reg_access_ctrl = &adev->gfx.rlc in gfx_v11_0_init_rlcg_reg_access_ctrl()
[all...] |
| H A D | gfx_v10_0.c | 3887 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
4078 if (adev->gfx.rlc.cs_data == NULL) in gfx_v10_0_get_csb_buffer()
4090 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v10_0_get_csb_buffer()
4121 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v10_0_rlc_fini()
4122 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v10_0_rlc_fini()
4123 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v10_0_rlc_fini()
4126 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v10_0_rlc_fini()
4127 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v10_0_rlc_fini()
4128 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v10_0_rlc_fini()
4135 reg_access_ctrl = &adev->gfx.rlc in gfx_v10_0_init_rlcg_reg_access_ctrl()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_rlc.c | 39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
84 * Allocate and setup value to save restore block of rlc.
97 &adev->gfx.rlc in amdgpu_gfx_rlc_init_sr()
[all...] |
| H A D | gfx_v6_0.c | 2057 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v6_0_cp_gfx_start()
2379 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list; in gfx_v6_0_rlc_init()
2380 adev->gfx.rlc.reg_list_size = in gfx_v6_0_rlc_init()
2383 adev->gfx.rlc.cs_data = si_cs_data; in gfx_v6_0_rlc_init()
2384 src_ptr = adev->gfx.rlc.reg_list; in gfx_v6_0_rlc_init()
2385 dws = adev->gfx.rlc.reg_list_size; in gfx_v6_0_rlc_init()
2386 cs_data = adev->gfx.rlc.cs_data; in gfx_v6_0_rlc_init()
2397 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev); in gfx_v6_0_rlc_init()
2398 dws = adev->gfx.rlc.clear_state_size + (256 / 4); in gfx_v6_0_rlc_init()
2402 &adev->gfx.rlc in gfx_v6_0_rlc_init()
2452 gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc) gfx_v6_0_update_rlc() argument
[all...] |
| H A D | amdgpu_ucode.c | 550 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
551 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, in amdgpu_ucode_init_single_fw()
554 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; in amdgpu_ucode_init_single_fw()
555 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, in amdgpu_ucode_init_single_fw()
558 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; in amdgpu_ucode_init_single_fw()
559 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, in amdgpu_ucode_init_single_fw()
562 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
563 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode, in amdgpu_ucode_init_single_fw()
566 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
567 memcpy(ucode->kaddr, adev->gfx.rlc in amdgpu_ucode_init_single_fw()
[all...] |
| H A D | gfx_v9_0.c | 1148 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
1158 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); in gfx_v9_0_init_rlc_ext_microcode()
1159 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); in gfx_v9_0_init_rlc_ext_microcode()
1162 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); in gfx_v9_0_init_rlc_ext_microcode()
1163 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); in gfx_v9_0_init_rlc_ext_microcode()
1166 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); in gfx_v9_0_init_rlc_ext_microcode()
1167 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); in gfx_v9_0_init_rlc_ext_microcode()
1168 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in gfx_v9_0_init_rlc_ext_microcode()
1307 !adev->gfx.rlc.is_rlc_v2_1)) in gfx_v9_0_check_if_need_gfxoff()
1449 adev->gfx.rlc in gfx_v9_0_init_rlc_microcode()
[all...] |
| H A D | gfx_v7_0.c | 2553 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
3299 /* allocate rlc buffers */ in gfx_v7_0_rlc_init()
3302 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3303 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3306 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3307 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3311 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3312 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3313 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3315 src_ptr = adev->gfx.rlc in gfx_v7_0_rlc_init()
3390 gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) gfx_v7_0_update_rlc() argument
[all...] |
| H A D | gfx_v8_0.c | 947 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
1076 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1078 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1080 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1082 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1084 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1086 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1088 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1090 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1092 adev->gfx.rlc in gfx_v8_0_init_microcode()
[all...] |
| H A D | gfx_v10_0.c | 3564 kfree(adev->gfx.rlc.register_list_format); in gfx_v10_0_free_microcode()
3603 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); in gfx_v10_0_init_rlc_ext_microcode()
3604 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); in gfx_v10_0_init_rlc_ext_microcode()
3607 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); in gfx_v10_0_init_rlc_ext_microcode()
3608 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); in gfx_v10_0_init_rlc_ext_microcode()
3611 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); in gfx_v10_0_init_rlc_ext_microcode()
3612 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); in gfx_v10_0_init_rlc_ext_microcode()
3613 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in gfx_v10_0_init_rlc_ext_microcode()
3622 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes); in gfx_v10_0_init_rlc_iram_dram_microcode()
3623 adev->gfx.rlc in gfx_v10_0_init_rlc_iram_dram_microcode()
[all...] |
| H A D | amdgpu_gfx.h | 256 struct amdgpu_rlc rlc; member
|
| H A D | amdgpu_ucode.h | 314 struct rlc_firmware_header_v1_0 rlc; member
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | evergreen.c | 4027 /* halt the rlc */ in evergreen_gpu_pci_config_reset()
4115 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4116 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4119 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4120 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4122 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4123 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4127 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4128 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4131 radeon_bo_unpin(rdev->rlc in sumo_rlc_fini()
[all...] |
| H A D | radeon_ucode.h | 215 struct rlc_firmware_header_v1_0 rlc; member
|
| H A D | cik.c | 4953 /* stop the rlc */ in cik_gpu_soft_reset()
5176 /* halt the rlc, disable cp internal ints */ in cik_gpu_pci_config_reset()
5817 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc) in cik_update_rlc() argument
5822 if (tmp != rlc) in cik_update_rlc()
5823 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6431 if (rdev->rlc.cp_table_ptr == NULL) in cik_init_cp_pg_table()
6435 dst_ptr = rdev->rlc.cp_table_ptr; in cik_init_cp_pg_table()
6627 if (rdev->rlc.cs_data) { in cik_init_gfx_cgpg()
6629 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6630 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc in cik_init_gfx_cgpg()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | evergreen.c | 4029 /* halt the rlc */ in evergreen_gpu_pci_config_reset()
4117 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4118 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4121 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4122 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4124 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4125 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4129 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4130 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4133 radeon_bo_unpin(rdev->rlc in sumo_rlc_fini()
[all...] |
| H A D | radeon_ucode.h | 215 struct rlc_firmware_header_v1_0 rlc; member
|
| H A D | cik.c | 4943 /* stop the rlc */ in cik_gpu_soft_reset()
5166 /* halt the rlc, disable cp internal ints */ in cik_gpu_pci_config_reset()
5806 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc) in cik_update_rlc() argument
5811 if (tmp != rlc) in cik_update_rlc()
5812 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6420 if (rdev->rlc.cp_table_ptr == NULL) in cik_init_cp_pg_table()
6424 dst_ptr = rdev->rlc.cp_table_ptr; in cik_init_cp_pg_table()
6616 if (rdev->rlc.cs_data) { in cik_init_gfx_cgpg()
6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc in cik_init_gfx_cgpg()
[all...] |
| /kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/fw/api/ |
| H A D | datapath.h | 450 * @rlc: RLC properties, &struct iwl_rlc_properties
457 struct iwl_rlc_properties rlc; member
|