Lines Matching refs:rlc
4943 /* stop the rlc */
5166 /* halt the rlc, disable cp internal ints */
5806 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)
5811 if (tmp != rlc)
5812 WREG32(RLC_CNTL, rlc);
6420 if (rdev->rlc.cp_table_ptr == NULL)
6424 dst_ptr = rdev->rlc.cp_table_ptr;
6616 if (rdev->rlc.cs_data) {
6618 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
6619 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
6620 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
6626 if (rdev->rlc.reg_list) {
6628 for (i = 0; i < rdev->rlc.reg_list_size; i++)
6629 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);
6637 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
6638 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);
6673 if (rdev->rlc.cs_data == NULL)
6681 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
6705 if (rdev->rlc.cs_data == NULL)
6717 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
6949 /* init rlc */
8307 /* allocate rlc buffers */
8310 rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;
8311 rdev->rlc.reg_list_size =
8314 rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;
8315 rdev->rlc.reg_list_size =
8319 rdev->rlc.cs_data = ci_cs_data;
8320 rdev->rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
8321 rdev->rlc.cp_table_size += 64 * 1024; /* GDS */
8324 DRM_ERROR("Failed to init rlc BOs!\n");