Lines Matching refs:rlc
4029 /* halt the rlc */
4117 if (rdev->rlc.save_restore_obj) {
4118 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4121 radeon_bo_unpin(rdev->rlc.save_restore_obj);
4122 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4124 radeon_bo_unref(&rdev->rlc.save_restore_obj);
4125 rdev->rlc.save_restore_obj = NULL;
4129 if (rdev->rlc.clear_state_obj) {
4130 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4133 radeon_bo_unpin(rdev->rlc.clear_state_obj);
4134 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4136 radeon_bo_unref(&rdev->rlc.clear_state_obj);
4137 rdev->rlc.clear_state_obj = NULL;
4141 if (rdev->rlc.cp_table_obj) {
4142 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4145 radeon_bo_unpin(rdev->rlc.cp_table_obj);
4146 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4148 radeon_bo_unref(&rdev->rlc.cp_table_obj);
4149 rdev->rlc.cp_table_obj = NULL;
4165 src_ptr = rdev->rlc.reg_list;
4166 dws = rdev->rlc.reg_list_size;
4170 cs_data = rdev->rlc.cs_data;
4174 if (rdev->rlc.save_restore_obj == NULL) {
4177 NULL, &rdev->rlc.save_restore_obj);
4184 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4189 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
4190 &rdev->rlc.save_restore_gpu_addr);
4192 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4198 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
4205 dst_ptr = rdev->rlc.sr_ptr;
4208 for (i = 0; i < rdev->rlc.reg_list_size; i++)
4228 radeon_bo_kunmap(rdev->rlc.save_restore_obj);
4229 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4235 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);
4237 rdev->rlc.clear_state_size = si_get_csb_size(rdev);
4238 dws = rdev->rlc.clear_state_size + (256 / 4);
4250 rdev->rlc.clear_state_size = dws;
4253 if (rdev->rlc.clear_state_obj == NULL) {
4256 NULL, &rdev->rlc.clear_state_obj);
4263 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4268 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
4269 &rdev->rlc.clear_state_gpu_addr);
4271 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4277 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
4284 dst_ptr = rdev->rlc.cs_ptr;
4288 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;
4291 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);
4295 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
4324 radeon_bo_kunmap(rdev->rlc.clear_state_obj);
4325 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4328 if (rdev->rlc.cp_table_size) {
4329 if (rdev->rlc.cp_table_obj == NULL) {
4330 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
4333 NULL, &rdev->rlc.cp_table_obj);
4341 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4347 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,
4348 &rdev->rlc.cp_table_gpu_addr);
4350 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4355 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr);
4364 radeon_bo_kunmap(rdev->rlc.cp_table_obj);
4365 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4414 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
4415 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5036 /* allocate rlc buffers */
5038 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
5039 rdev->rlc.reg_list_size =
5041 rdev->rlc.cs_data = evergreen_cs_data;
5044 DRM_ERROR("Failed to init rlc BOs!\n");