Lines Matching refs:rlc
4027 /* halt the rlc */
4115 if (rdev->rlc.save_restore_obj) {
4116 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4119 radeon_bo_unpin(rdev->rlc.save_restore_obj);
4120 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4122 radeon_bo_unref(&rdev->rlc.save_restore_obj);
4123 rdev->rlc.save_restore_obj = NULL;
4127 if (rdev->rlc.clear_state_obj) {
4128 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4131 radeon_bo_unpin(rdev->rlc.clear_state_obj);
4132 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4134 radeon_bo_unref(&rdev->rlc.clear_state_obj);
4135 rdev->rlc.clear_state_obj = NULL;
4139 if (rdev->rlc.cp_table_obj) {
4140 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4143 radeon_bo_unpin(rdev->rlc.cp_table_obj);
4144 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4146 radeon_bo_unref(&rdev->rlc.cp_table_obj);
4147 rdev->rlc.cp_table_obj = NULL;
4163 src_ptr = rdev->rlc.reg_list;
4164 dws = rdev->rlc.reg_list_size;
4168 cs_data = rdev->rlc.cs_data;
4172 if (rdev->rlc.save_restore_obj == NULL) {
4175 NULL, &rdev->rlc.save_restore_obj);
4182 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false);
4187 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM,
4188 &rdev->rlc.save_restore_gpu_addr);
4190 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4196 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr);
4203 dst_ptr = rdev->rlc.sr_ptr;
4206 for (i = 0; i < rdev->rlc.reg_list_size; i++)
4226 radeon_bo_kunmap(rdev->rlc.save_restore_obj);
4227 radeon_bo_unreserve(rdev->rlc.save_restore_obj);
4233 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);
4235 rdev->rlc.clear_state_size = si_get_csb_size(rdev);
4236 dws = rdev->rlc.clear_state_size + (256 / 4);
4248 rdev->rlc.clear_state_size = dws;
4251 if (rdev->rlc.clear_state_obj == NULL) {
4254 NULL, &rdev->rlc.clear_state_obj);
4261 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false);
4266 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM,
4267 &rdev->rlc.clear_state_gpu_addr);
4269 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4275 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr);
4282 dst_ptr = rdev->rlc.cs_ptr;
4286 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;
4289 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);
4293 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
4322 radeon_bo_kunmap(rdev->rlc.clear_state_obj);
4323 radeon_bo_unreserve(rdev->rlc.clear_state_obj);
4326 if (rdev->rlc.cp_table_size) {
4327 if (rdev->rlc.cp_table_obj == NULL) {
4328 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size,
4331 NULL, &rdev->rlc.cp_table_obj);
4339 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false);
4345 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM,
4346 &rdev->rlc.cp_table_gpu_addr);
4348 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4353 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr);
4362 radeon_bo_kunmap(rdev->rlc.cp_table_obj);
4363 radeon_bo_unreserve(rdev->rlc.cp_table_obj);
4412 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
4413 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
5035 /* allocate rlc buffers */
5037 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list;
5038 rdev->rlc.reg_list_size =
5040 rdev->rlc.cs_data = evergreen_cs_data;
5043 DRM_ERROR("Failed to init rlc BOs!\n");